Effect of Additives in an Electrolyte on Mechanical Properties of Electrolytic Copper Foil

The effect of additives in electrolyte on mechanical properties of electrolytic copper foil was investigated. Bis-(3-sulfopropyl)-disulfide disodium salt (SPS), animal protein of low molecular (PBF) and hydroxyethyl cellulose (HEC) were added in electrolyte as additives. The additive amount of SPS was changed in this study. The addition of SPS is effective to improve tensile strength and hardness of electrolytic copper foil. With increasing the additive amount of SPS, the grain of electrolytic copper became finer and thus its hardness and elastic modulus increased. On the other hand, fatigue properties improved when the additive amount of SPS decreased and the grain size of electrolytic copper became relative large.

Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

A Methodology for High Cycle Fatigue Characterization of Lead-Free Interconnects Under Simultaneous Harsh Environments of High Temperature and Vibration

Current trends in the automotive industry warrant a variety of electronics for improved control, safety, efficiency and entertainment. Many of these electronic systems like engine control units, variable valve sensor, crankshaft-camshaft sensors are located under-hood. Electronics installed in under-hood applications are subjected simultaneously to mechanical vibrations and thermal loads. Typical failure modes caused by vibration induced high cycle fatigue include solder fatigue, copper trace or lead fracture. The solder interconnects accrue damage much faster when vibrated at elevated temperatures. Industry migration to lead-free solders has resulted in a proliferation of a wide variety of solder alloy compositions. Presently, the literature on mechanical behavior of lead-free alloys under simultaneous harsh environment of high-temperature vibration is sparse. In this paper, the reduction in stiffness of the PCB with temperature has been demonstrated by measuring the shift in natural frequencies. The test vehicle consisting of a variety of lead-free SAC305 daisy chain components including BGA, QFP, SOP and TSOPs has been tested to failure by subjecting it to two elevated temperatures and harmonic vibrations at the corresponding first natural frequency. The test matrix includes three test temperatures of 25C, 75C and 125C and simple harmonic vibration amplitude of 10G which are values typical in automotive testing. PCB deflection has been shown to increase with increase in temperature. The full field strain has been extracted using high speed cameras operating at 100,000 fps in conjunction with digital image correlation. Material properties of the PCB at test temperatures have been measured using tensile tests and dynamic mechanical analysis. FE simulation using global-local finite element models is thus correlated with the system characteristics such as modal shapes, natural frequencies and displacement amplitudes for every temperature. The solder level stresses have been extracted from the sub-models. Stress amplitude versus cycles to failure curves are obtained at all the three test temperatures. A comparison of failure modes for different surface mount packages at elevated test temperatures and vibration has been presented in this study.

Dynamic Analysis of Thin Glass Under Ball Drop Impact With New Metrics

Response of brittle plate to impact loads has been the subject of many research studies [1–7]. Specifically, glass presents a wide variety of applications in daily life, and helps to protect the displays of smartphones, tablets, PCs, and TVs from everyday wear and tear. Therefore, the necessity of glass to resist scratches, drop impacts, and bumps from everyday use leads to the importance of investigation of the glass response under dynamic impact loading. The ball drop test has been applied in the past, specifying an energy threshold as a prediction metric. Use of energy as the key parameter in impact testing is limited, since it does not account for the time spent in contact during the impact event. This study attempts to establish a reliable metric for impact testing based on a momentum change threshold. The deformation and the strain of the glass will be obtained by the Digital Image Correlation (DIC) system, while the rebound velocity will be measured with the high speed cameras. The global and local measurements are conducted to verify the accuracy of the experimental results. Finally, the FEA model is developed using ANSYS/LS-DYNA to provide a comprehensive understanding of the dynamic response of the glass. Excellent correlation in deflection is obtained between the measurements and predictions.

Highly Sensitive 2D Strain Sensor Using Carbon Nanotube

A new highly sensitive strain measurement method has been developed by applying the strain-induced change of the electronic conductivity of CNTs. It is reported that most multi-walled carbon nanotubes (MWCNTs) show metallic conductivity and they are rather cheap comparing with single-walled carbon nanotubes (SWCNTs). However, it was found that the electric conductivity of MWCNTs changes drastically under uniaxial strain because of the drastic change of their band gap. Therefore, the authors have developed a highly sensitive strain sensor which can detect the local strain distribution by using MWCNTs. In order to design a new sensor using MWCNT, it is very important to control the shape of the MWCNTs under strain. Thus, a method for controlling the shape of the MWCNTs was developed by applying a chemical vapor deposition (CVD) technique. It was found that the shape of the grown MWCNT could be controlled by changing the average thickness of the catalyst and the deposition temperature of the MWCNT. The electrical resistance of the grown MWCNT changed almost linearly with the applied strain, and the maximum strain sensitivity obtained under the application of uniaxial strain was about 10%/1000-μstrain (gauge factor: 100). A two-dimensional strain sensor, which consists of area-arrayed fine bundles of MWCNTs, has been developed by applying MEMS technology. Under the application of compressive strain, the electric resistance was confirmed to increase almost linearly with the applied strain.

Simulations of Deformation and Stress During Copper Wirebond on ULK Chips

In this paper, we develop a multi-level modeling procedure for copper wirebonding that provides insights into (a) deformation and stress in wire, pad, and die (b) an assessment of the risk of ULK fracture during impact stage and ultrasonic vibration steps. First, we construct a nonlinear, dynamic finite element model (global) to study the mechanical responses of wire, pad, and the underlying ULK stacks during the impact stage and the last cycle of ultrasonic vibration in copper wirebonding. Specifically, these process steps are modeled through prescribing touch down and in-plane oscillatory motions on capillary, which result in dissimilar critical states of stress locally in the ULK stacks. Next, we develop a isogeometric model (local) for a generic configuration of ULK stacks with eight levels of metallization by composing the geometric primitives representing ILD layers, copper lines/vias, as well as the material interfaces following the Hierarchical Partition of Unity Field Composition technique. The description for material moduli in the entire ULK stacks is further enriched with a bi-linear damage law. The critical states of stress obtained in the global wirebond model are then converted into boundary conditions for the local ILD model under plane strain condition to simulate the crack initiation in the ULK stacks. We observe, from the simulation results, potential crack initiation sites along vertical /horizontal interfaces in the ULK stacks due to local compressive/tensile loading during impact/vibration step, respectively.

Analytical Modeling of Temperature Distribution in Interposer-Based Microelectronic Systems

Heterogeneous integration in microelectronic systems using interposer technology has attracted significant research attention in the past few years. Interposer technology is based on stacking of several heterogeneous chips on a common carrier substrate, also referred to as the interposer. Compared to other technologies such as System-on-Chip (SoC) or System-in-Package (SiP), interposer-based integration offers several technological advantages. However, the thermal management of an interposer-based system is not well understood. The presence of multiple heat sources in various die and the interposer itself needs to be accounted for in any effective thermal model. While a finite-element based simulation may provide a reasonable temperature prediction tool, an analytical solution is highly desirable for understanding the fundamentals of the heat transfer process in interposers. In this paper, we describe our recent work on analytical modeling of heat transfer in interposer-based microelectronic systems. The basic governing energy conservation equations are solved to derive analytical expressions for the temperature distribution in an interposer-based microelectronic system. These solutions are combined with an iterative approach to provide the three-dimensional temperature field in an interposer. Results are in excellent agreement with finite-element solutions. The analytical model is utilized to study the effect of various parameters on the temperature field in an interposer system. Results from this work may be helpful in the thermal design of microelectronic systems containing interposers.

3D Stacks of Microprocessors and Memories With Backside Two-Phase Multi-Microchannel Cooler

For the next generation of high performance computers, the new challenges are to shorten the distance for transporting data (to accelerate the transfer of information) between multi-microprocessors and memories, and to cool these electronic components despite the increased heat flux that results from increased transistor density. Recent technological advances show a tendency for the development of 3D integrated circuit stacked architectures with interlayer cooling (multi-microchannels in the silicon layers). However, huge challenges exist in such design/concept, i.e. flow distribution to hundreds microchannels distributed in the different interlayers, thermo-hydrodynamic and geometrical limitations, manufacturing etc. 3D-ICs with interlayer cooling are still about a decade away, so a viable shorter term goal is 3D stacks with backside cooling, taking advantage of Si layers now able to be thineer down to only 50 μm thickness. Thus, the present work presents thermo-hydrodynamic simulations for 3D stacks considering only a backside cooler, which simplifies considerably the assembly and guarantees a high level of reliability. In summary, the results showed that this concept is thermally feasible and potentially that interlayer microchannels (between stacks) will not be necessary.

A Fracture Mechanics Based Parametric Study of the Copper-to-Copper Direct Thermo-Compression Bonded Interface Using Finite Element Method

Through-silicon via (TSV) technology is expected to overcome the limitations of I/O density and helps in enhancing system performance of conventional flip chip packages. One of the challenges for producing reliable TSV packages is the stacking and joining of thin wafers or dies. In the case of the conventional solder interconnections, many reliability issues arise at the interface between solder and copper bump. As an alternative solution, Cu-Cu direct thermo-compression bonding (CuDB) is a possible option to enable three-dimension (3D) package integration. CuDB has several advantages over the solder based micro bump joining, such as reduction in soldering process steps, enabling higher interconnect density, enhanced thermal conductivity and decreased concerns about intermetallic compounds (IMC) formation. Critical issue of CuDB is bonding interface condition. After the bonding process, Cu-Cu direct bonding interface is obtained. However, several researchers have reported small voids at the bonded interface. These defects can act as an initial crack which may lead to eventual fracture of the interface. The fracture could happen due to the thermal expansion coefficient (CTE) mismatch between the substrate and the chip during the postbonding process, board level reflow or thermal cycling with large temperature changes. In this study, a quantitative assessment of the energy release rate has been made at the CuDB interface during temperature change finite element method (FEM). A parametric study is conducted to analyze the impact of the initial crack location and the material properties of surrounding materials. Finally, design recommendations are provided to minimize the probability of interfacial delamination in CuDB.

Analytic Optimization of Cost Effective Thermoelectric Generation on Top of Rankine Cycle

Thermoelectric (TE) generators have a potential advantage of the wide applicable temperature range by a proper selection of materials. In contrast, a steam turbine (ST) as a Rankine cycle thermodynamic generator is limited up to more or less 630 °C for the heat source. Unlike typical waste energy recovery systems, we propose a combined system placing a TE generator on top of a ST Rankine cycle generator. This system produces an additional power from the same energy source comparing to a stand-alone steam turbine system. Fuel efficiency is essential both for the economic efficiency and the ecological friendliness, especially for the global warming concern on the carbon dioxide (CO2) emission. We report our study of the overall performance of the combined system with primarily focusing on the design parameters of thermoelectric generators. The steam temperature connecting two individual generators gives a trade-off in the system design. Too much lower the temperature reduces the ST performance and too much higher the temperature reduces the temperature difference across the TE generator hence reduces the TE performance. Based on the analytic modeling, the optimum steam temperature to be designed is found near at the maximum power design of TE generator. This optimum point changes depending on the hours-of-operation. It is because the energy conversion efficiency directly connects to the fuel consumption rate. As the result, physical upper-limit temperature of steam for ST appeared to provide the best fuel economy. We also investigated the impact of improving the figure-of-merit (ZT) of TE materials. As like generic TE engines, reduction of thermal conductivity is the most influential parameter for improvement. We also discuss the cost-performance. The combined system provides the payback per power output at the initial and also provides the significantly better energy economy [$/KWh].