Experimental Demonstration of 20-Gbit/s Data Transmission Link using a 1.1 km Elliptical-Core Few-Mode Fiber assisted by Mapping from Conventional Amplitude Modulation to Spatial Mode Modulation

2017 ◽  
Author(s):  
Qi Mo ◽  
Long Zhu ◽  
Andong Wang ◽  
Jun Liu ◽  
Cheng Du ◽  
...  
Keyword(s):  
Amplitude Modulation ◽  
Data Transmission ◽  
Spatial Mode ◽  
Experimental Demonstration ◽  
Elliptical Core ◽  
Transmission Link

Experimental demonstration of high-speed data transmission based on Gaussian pulses for IR-UWB radio-over-fiber systems

2017 ◽  
Author(s):  
Elizaveta P. Grakhova ◽  
Albert Kh. Sultanov ◽  
Irina L. Vinogradova ◽  
Ivan K. Meshkov ◽  
Anna V. Andrianova ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Radio Over Fiber ◽  
Experimental Demonstration ◽  
High Speed Data ◽  
Uwb Radio ◽  
Speed Data Transmission

scholarly journals Design of Spatial-Mode (De)Multiplexer for Few-Mode Fibers Based on a Cyclically Used Michelson-Like Interferometer

2020 ◽  
Vol 10 (23) ◽  
pp. 8584
Author(s):  
Xesús Prieto-Blanco ◽  
Carlos Montero-Orille ◽  
Vicente Moreno de Las Cuevas ◽  
María C. Nistal ◽  
Dolores Mouriz ◽  
...  
Keyword(s):  
Optical Fibers ◽  
Efficient Method ◽  
Optical Communications ◽  
Data Rate ◽  
Phase Plate ◽  
Spatial Mode ◽  
Optical Elements ◽  
Polarization Insensitive ◽  
Elliptical Core

Few mode optical fibers are a promising way to continue increasing the data rate in optical communications. However, an efficient method to launch and extract separately each mode is essential. The design of a interferometric spatial mode (de)multiplexer for few mode optical fibers is presented. It is based on a single Michelson-like interferometer which consists of standard optical elements and has a reflective image inverter in one arm. Particular care has been taken in its design so that both polarizations behave the same. Moreover, this interferometer can process several pairs of modes simultaneously. The multiplexer also consists of: a phase plate, focusing optics at both ports of the interferometer and elliptical core fibers to recirculate some outputs. It can multiplex ten spatial and polarization modes and it presents low losses and no intrinsic crosstalk between modes. Additionally, it is polarization insensitive, achromatic, compact and inexpensive. The same system can work as a demultiplexer when used in reverse. In this case, both the losses and the crosstalk remain very low. Similar designs that perform other functions, like an add-drop mode multiplexing, are also suggested.

scholarly journals Analysis and experimental demonstration of spatial mode selection in a coherently combined fiber laser

2020 ◽  
Vol 28 (2) ◽  
pp. 1854
Author(s):  
Erik Tilseth ◽  
W. Minster Kunkel ◽  
James R. Leger
Keyword(s):  
Fiber Laser ◽  
Mode Selection ◽  
Spatial Mode ◽  
Experimental Demonstration

scholarly journals 100 Gb/s single VCSEL data transmission link

2012 ◽  
Author(s):  
R. Rodes ◽  
J. Estaran ◽  
B. Li ◽  
M. Muller ◽  
J. B. Jensen ◽  
...  
Keyword(s):  
Data Transmission ◽  
Transmission Link

FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System

2014 ◽  
Vol 3 (2) ◽  
pp. 76
Author(s):  
Manoj Kumar A ◽  
R V Nadagouda ◽  
R Jegan
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Data Transmission ◽  
Modulation Scheme ◽  
Link Performance ◽  
Ethernet Controller ◽  
Transmission Link ◽  
Spacecraft Data ◽  
To Receive ◽  
Ber Analysis

Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.

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