scholarly journals DVFS Algorithms of GPU and Memory for Mobile GPGPU Applications: A case study

2018 ◽  
Vol 7 (3) ◽  
pp. 1918
Author(s):  
SeongKi Kim ◽  
Seok-Kyoo Kim
Keyword(s):  
Energy Consumption ◽  
Graphics Processing Unit ◽  
Power Saving ◽  
General Purpose ◽  
Processing Unit ◽  
Performance Per Watt ◽  
Efficiency Performance ◽  
Dynamic Voltage ◽  
Graphics Processing

Although both OpenCL and RenderScript have allowed the General-Purpose Graphics Processing Unit (GPGPU) to be used even for mobile GPUs, it is still difficult for mobile applications to use the GPGPU for several reasons. One of the reasons is that mobile devices place restrictions on GPU performance through power-saving technologies such as Dynamic Voltage and Frequency Scaling (DVFS). DVFS tries to control the balance between performance and energy consumption based on the application’s requirements. This technology has been successful in many cases and is widely used; however, it significantly decreases the performance of GPGPU applications. In this paper, we propose novel DVFS algorithms for GPU and memory when the GPGPU applications run. The suggested algorithms decreased the energy consumption by more than 0.7 times without any algorithm changes, and improved the energy efficiency (performance per watt) by more than 3.42 times in comparison with the conventional interval-based algorithm.

Comprehensive regression-based model to predict performance of general-purpose graphics processing unit

2019 ◽  
Vol 23 (2) ◽  
pp. 1505-1516 ◽  
Author(s):  
Mohammad Hossein Shafiabadi ◽  
Hossein Pedram ◽  
Midia Reshadi ◽  
Akram Reza
Keyword(s):  
Graphics Processing Unit ◽  
General Purpose ◽  
Processing Unit ◽  
Graphics Processing

AN EVALUATION OF MULTIPLE FEED-FORWARD NETWORKS ON GPUs

2011 ◽  
Vol 21 (01) ◽  
pp. 31-47 ◽  
Author(s):  
NOEL LOPES ◽  
BERNARDETE RIBEIRO
Keyword(s):  
Graphics Processing Unit ◽  
Parallel Implementation ◽  
Low Cost ◽  
Back Propagation ◽  
General Purpose ◽  
Training System ◽  
Graphics Hardware ◽  
Processing Unit ◽  
Data Parallel ◽  
Graphics Processing

The Graphics Processing Unit (GPU) originally designed for rendering graphics and which is difficult to program for other tasks, has since evolved into a device suitable for general-purpose computations. As a result graphics hardware has become progressively more attractive yielding unprecedented performance at a relatively low cost. Thus, it is the ideal candidate to accelerate a wide variety of data parallel tasks in many fields such as in Machine Learning (ML). As problems become more and more demanding, parallel implementations of learning algorithms are crucial for a useful application. In particular, the implementation of Neural Networks (NNs) in GPUs can significantly reduce the long training times during the learning process. In this paper we present a GPU parallel implementation of the Back-Propagation (BP) and Multiple Back-Propagation (MBP) algorithms, and describe the GPU kernels needed for this task. The results obtained on well-known benchmarks show faster training times and improved performances as compared to the implementation in traditional hardware, due to maximized floating-point throughput and memory bandwidth. Moreover, a preliminary GPU based Autonomous Training System (ATS) is developed which aims at automatically finding high-quality NNs-based solutions for a given problem.

scholarly journals GPU-accelerated alignment of bisulfite-treated short-read sequences

2017 ◽  
Author(s):  
Richard Wilton ◽  
Xin Li ◽  
Andrew P. Feinberg ◽  
Alexander S. Szalay
Keyword(s):  
Dna Sequences ◽  
Graphics Processing Unit ◽  
General Purpose ◽  
Processing Unit ◽  
Short Read ◽  
Wide Range ◽  
Programming Logic ◽  
Short Read Aligner ◽  
Graphics Processing ◽  
Better Than

AbstractThe alignment of bisulfite-treated DNA sequences (BS-seq reads) to a large genome involves a significant computational burden beyond that required to align non-bisulfite-treated reads. In the analysis of BS-seq data, this can present an important performance bottleneck that can potentially be addressed by appropriate software-engineering and algorithmic improvements. One strategy is to integrate this additional programming logic into the read-alignment implementation in a way that the software becomes amenable to optimizations that lead to both higher speed and greater sensitivity than can be achieved without this integration.We have evaluated this approach using Arioc, a short-read aligner that uses GPU (general-purpose graphics processing unit) hardware to accelerate computationally-expensive programming logic. We integrated the BS-seq computational logic into both GPU and CPU code throughout the Arioc implementation. We then carried out a read-by-read comparison of Arioc's reported alignments with the alignments reported by the most widely used BS-seq read aligners. With simulated reads, Arioc's accuracy is equal to or better than the other read aligners we evaluated. With human sequencing reads, Arioc's throughput is at least 10 times faster than existing BS-seq aligners across a wide range of sensitivity settings.The Arioc software is available at https://github.com/RWilton/Arioc. It is released under a BSD open-source license.

scholarly journals Analysis of Fast Fourier Transformations algorithm for CUDA Architecture

2012 ◽  
Vol 53 ◽  
Author(s):  
Beatričė Andziulienė ◽  
Evaldas Žulkas ◽  
Audrius Kuprinavičius
Keyword(s):  
Graphics Processing Unit ◽  
General Purpose ◽  
Fast Fourier Transformation ◽  
Processing Unit ◽  
Data Allocation ◽  
Analysis Method ◽  
Central Processing ◽  
Execution Speed ◽  
Cuda Architecture ◽  
Graphics Processing

In this work Fast Fourier transformation algorithm for general purpose graphics processing unit processing (GPGPU) is discussed. Algorithm structure and individual stages performance were analysed. With performance analysis method algorithm distribution and data allocation possibilities were determined, depending on algorithm stages execution speed and algorithm structure. Ratio between CPU and GPU execution during Fast Fourier transform signal processing was determined using computer-generated data with frequency. When adopting CPU code for CUDA execution, it not becomes more complex, even if stream procesor parallelization and data transfering algorith stages are considered. But central processing unit serial execution).

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