Action: A New Metric for Evaluating the Energy Efficiency on High Performance Computing Platforms (ranked on Green500 List)

The need for new and more reliable metrics is always in demand. In this paper, a new metric is proposed for the evaluation of high performance computing platforms in conjunction with their energy consumption. The aim of the new metric is to reliably compare different HPC systems concerning their energy efficiency. The metric provides a mean to rank supercomputers of similar capabilities, avoiding the misleading results of metrics like performance-per-watt, currently used for ranking systems, as in the Green500 list, where systems with totally different sizes and capabilities are ranked consecutively. An example of this misuse for two adjacent systems in the Green500 list, is discussed. A comparative study for the energy efficiency of three high performance computing platforms, with different architectures, using the proposed metric is presented.

Low Energy Consumption on Post-Moore Platforms for HPC Research

The increase in computational capacities has helped in the exploration, production and research process, this has allowed the use of applications that were infeasible years ago. This increase brings us a new Era (known as Post-Moore Era) and a wide range of promising devices, devices such as Single Board Computers (SBC) or Personal Computers (PC) that achieve performance that a decade ago was only found on a Server. This work presents high performance computing devices with low monetary cost and low energy cost that meet the needs for the development of research in Artificial Intelligent (AI) applications, in-situ data analysis and simulations that can be implemented on a large scale, these devices are compared in different tests, presenting advantages such as its performance per watt consumed, smart form, among others.

Real-Time FPGA Accelerated Stereo Matching for Temporal Statistical Pattern Projector Systems

The presented paper describes a hardware-accelerated field programmable gate array (FPGA)–based solution capable of real-time stereo matching for temporal statistical pattern projector systems. Modern 3D measurement systems have seen an increased use of temporal statistical pattern projectors as their active illumination source. The use of temporal statistical patterns in stereo vision systems includes the advantage of not requiring information about pattern characteristics, enabling a simplified projector design. Stereo-matching algorithms used in such systems rely on the locally unique temporal changes in brightness to establish a pixel correspondence between the stereo image pair. Finding the temporal correspondence between individual pixels in temporal image pairs is computationally expensive, requiring GPU-based solutions to achieve real-time calculation. By leveraging a high-level synthesis approach, matching cost simplification, and FPGA-specific design optimizations, an energy-efficient, high throughput stereo-matching solution was developed. The design is capable of calculating disparity images on a 1024 × 1024(@291 FPS) input image pair stream at 8.1 W on an embedded FPGA platform (ZC706). Several different design configurations were tested, evaluating device utilization, throughput, power consumption, and performance-per-watt. The average performance-per-watt of the FPGA solution was two times higher than in a GPU-based solution.

Hardware/Software Co-Design of Fractal Features Based Fall Detection System

Falls are a leading cause of death in older adults and result in high levels of mortality, morbidity and immobility. Fall Detection Systems (FDS) are imperative for timely medical aid and have been known to reduce death rate by 80%. We propose a novel wearable sensor FDS which exploits fractal dynamics of fall accelerometer signals. Fractal dynamics can be used as an irregularity measure of signals and our work shows that it is a key discriminant for classification of falls from other activities of life. We design, implement and evaluate a hardware feature accelerator for computation of fractal features through multi-level wavelet transform on a reconfigurable embedded System on Chip, Zynq device for evaluating wearable accelerometer sensors. The proposed FDS utilises a hardware/software co-design approach with hardware accelerator for fractal features and software implementation of Linear Discriminant Analysis on an embedded ARM core for high accuracy and energy efficiency. The proposed system achieves 99.38% fall detection accuracy, 7.3× speed-up and 6.53× improvements in power consumption, compared to the software only execution with an overall performance per Watt advantage of 47.6×, while consuming low reconfigurable resources at 28.67%.

DVFS Algorithms of GPU and Memory for Mobile GPGPU Applications: A case study

Although both OpenCL and RenderScript have allowed the General-Purpose Graphics Processing Unit (GPGPU) to be used even for mobile GPUs, it is still difficult for mobile applications to use the GPGPU for several reasons. One of the reasons is that mobile devices place restrictions on GPU performance through power-saving technologies such as Dynamic Voltage and Frequency Scaling (DVFS). DVFS tries to control the balance between performance and energy consumption based on the application’s requirements. This technology has been successful in many cases and is widely used; however, it significantly decreases the performance of GPGPU applications. In this paper, we propose novel DVFS algorithms for GPU and memory when the GPGPU applications run. The suggested algorithms decreased the energy consumption by more than 0.7 times without any algorithm changes, and improved the energy efficiency (performance per watt) by more than 3.42 times in comparison with the conventional interval-based algorithm.

Engineering QoS and Energy Saving in the Delivery of ICT Services

ICT service-providers are to daily face the problem of delivering ICT services (data processing (Dp) and/or telecommunication (Tlc) services) assuring the best compromise between Quality of Service (QoS) and Energy Optimization. Indeed, any operation of saving energy involves waste in the QoS. This holds both for Dp and for Tlc services. This paper introduces models the providers may use to support their decisions in the delivery of ICT services. Dp systems totalize millions of servers all over the world that need to be electrically powered. Dp systems are also used in the government of Tlc systems, which also require Tlc-specific power, both for mobile networks and for wired networks. Research is thus expected to investigate into methods to reduce ICT power consumption. This paper investigates ICT power management strategies that look at compromises between energy saving and QoS. Various optimizing ICT power management policies are studied that optimize the ICT power consumption (minimum absorbed Watts), the ICT performance (minimum response-time), and the ICT performance-per-Watt.