scholarly journals Torus–Connected Cycles: A Simple and Scalable Topology for Interconnection Networks

2015 ◽  
Vol 25 (4) ◽  
pp. 723-735 ◽  
Author(s):  
Antoine Bossard ◽  
Keiichi Kaneko
Keyword(s):  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Hamiltonian Path ◽  
Small Diameter ◽  
Critical Parameters ◽  
Time Optimal ◽  
Point To Point ◽  
Torus Networks

Abstract Supercomputers are today made up of hundreds of thousands of nodes. The interconnection network is responsible for connecting all these nodes to each other. Different interconnection networks have been proposed; high performance topologies have been introduced as a replacement for the conventional topologies of recent decades. A high order, a low degree and a small diameter are the usual properties aimed for by such topologies. However, this is not sufficient to lead to actual hardware implementations. Network scalability and topology simplicity are two critical parameters, and they are two of the reasons why modern supercomputers are often based on torus interconnection networks (e.g., Fujitsu K, IBM Sequoia). In this paper we first describe a new topology, torus-connected cycles (TCCs), realizing a combination of a torus and a ring, thus retaining interesting properties of torus networks in addition to those of hierarchical interconnection networks (HINs). Then, we formally establish the diameter of a TCC, and deduce a point-to-point routing algorithm. Next, we propose routing algorithms solving the Hamiltonian cycle problem, and, in a two dimensional TCC, the Hamiltonian path one. Correctness and complexities are formally proved. The proposed algorithms are time-optimal.

BROADCASTING IN BUS INTERCONNECTION NETWORKS

2000 ◽  
Vol 01 (02) ◽  
pp. 73-94
Author(s):  
A. FERREIRA ◽  
A. GOLDMAN ◽  
S. W. SONG
Keyword(s):  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Parallel Architectures ◽  
Interprocessor Communication ◽  
Efficient Manner ◽  
Graph Theoretic ◽  
Communication Algorithms ◽  
Communication Links ◽  
Point To Point

In most distributed memory MIMD multiprocessors, processors are connected by a point-to-point interconnection network, usually modeled by a graph where processors are nodes and communication links are edges. Since interprocessor communication frequently constitutes serious bottlenecks, several architectures were proposed that enhance point-to-point topologies with the help of multiple bus systems so as to improve the communication efficiency. In this paper we study parallel architectures where the communication means are constituted solely by buses. These architectures can use the power of bus technologies, providing a way to interconnect much more processors in a simple and efficient manner. We present the hyperpath, hypergrid, hyperring, and hypertorus architectures, which are the bus-based versions of the well used point-to-point interconnection networks. Using (hyper) graph theoretic concepts to model inter-processor communication in such networks, we give optimal algorithms for broadcasting a message from one processor to all the others. For deriving high performance communication patterns we developed a new tool called simplification. The idea is to construct a graph, to be called representative graph, from the original hyper-topology, in such a way that it will become easy to describe and perform communication schemes to the former that will fit to the latter, because the simplification concept also allows us to partially use some already known communication algorithms for usual networks.

scholarly journals Variable Expanding Structure for Data Center Interconnection Networks

2021 ◽  
Vol 25 (1) ◽  
pp. 13-22
Author(s):  
Jianfei Zhang ◽  
◽  
Yuchen Jiang ◽  
Yan Liu
Keyword(s):  
Data Center ◽  
Interconnection Networks ◽  
High Performance ◽  
Large Scale ◽  
Data Centers ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Address Space ◽  
Novel Structure ◽  
Large Scale Data Processing

Data centers are fundamental facilities that support high-performance computing and large-scale data processing. To guarantee that a data center can provide excellent properties of expanding and routing, the interconnection network of a data center should be designed elaborately. Herein, we propose a novel structure for the interconnection network of data centers that can be expanded with a variable coefficient, also known as a variable expanding structure (VES). A VES is designed in a hierarchical manner and built iteratively. A VES can include hundreds of thousands and millions of servers with only a few layers. Meanwhile, a VES has an extremely short diameter, which implies better performance on routing between every pair of servers. Furthermore, we design an address space for the servers and switches in a VES. In addition, we propose a construction algorithm and routing algorithm associated with the address space. The results and analysis of simulations verify that the expanding rate of a VES depends on three factors: n, m, and k where the n is the number of ports on a switch, the m is the expanding speed and the k is the number of layers. However, the factor m yields the optimal effect. Hence, a VES can be designed with factor m to achieve the expected expanding rate and server scale based on the initial planning objectives.

A New Unicast Routing Algorithm for Hyper Hexa-Cell Interconnection Networks

2017 ◽  
Vol 8 (3) ◽  
pp. 45-57
Author(s):  
Jehad Ahmed Al-Sadi
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Optimal Path ◽  
Destination Node ◽  
Topological Properties ◽  
Unicast Routing ◽  
Cell Topology ◽  
Store And Forward ◽  
Point To Point

The Hyper Hexa-Cell topology; HHC for short; is a new interconnection network topology that has many attractive topological properties compared to other traditional topologies. There have been a number of studies in the literature on the HHC to explore the promising topological properties of this topology. Furthermore, other studies extend this topology by combining it with OTIS technology to produce a new version called OHHC. We have found that there is a lake of presenting any point to point routing algorithm for the HHC, although there were some efforts on building routing algorithms for the OHHC. To cover this shortage, this paper introduces a new unicast routing algorithm for the HHC. The new routing algorithm for the HHC uses store-and-forward technique which allows a message to be transmitted through a path from the source node to the destination node. In addition to presenting the routing algorithm, we present an example to explore the algorithm steps and also an enhancement on the routing algorithm to apply adaptively on the routing based on parameterized criteria. Finally, we present a theoretical theorem to prove that the algorithm routes any message from any source to any destination via an optimal path.

THE CUBE-OF-RINGS INTERCONNECTION NETWORK

1998 ◽  
Vol 09 (01) ◽  
pp. 25-37 ◽  
Author(s):  
THOMAS J. CORTINA ◽  
ZHIWEI XU
Keyword(s):  
Graph Theory ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Parallel Computers ◽  
Closed Form Expression ◽  
Form Expression ◽  
Graph Theoretic ◽  
Basic Graph

We present a family of interconnection networks named the Cube-Of-Rings (COR) networks along with their basic graph-theoretic properties. Aspects of group graph theory are used to show the COR networks are symmetric and optimally fault tolerant. We present a closed-form expression of the diameter and optimal one-to-one routing algorithm for any member of the COR family. We also discuss the suitability of the COR networks as the interconnection network of scalable parallel computers.

FACILITATING HIGH-PERFORMANCE IMAGE ANALYSIS ON REDUCED HYPERCUBE (RH) PARALLEL COMPUTERS

1995 ◽  
Vol 09 (04) ◽  
pp. 679-698 ◽  
Author(s):  
SOTIRIOS G. ZIAVRAS ◽  
MICHALIS A. SIDERAS
Keyword(s):  
Image Analysis ◽  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Parallel Computers ◽  
Number Of Publications ◽  
Low Dimensional ◽  
High Level ◽  
The Cost ◽  
Cube Connected Cycles

The direct binary hypercube interconnection network has been very popular for the design of parallel computers, because it provides a low diameter and can emulate efficiently the majority of the topologies frequently employed in the development of algorithms. The last fifteen years have seen major efforts to develop image analysis algorithms for hypercube-based parallel computers. The results of these efforts have culminated in a large number of publications included in prestigious scholarly journals and conference proceedings. Nevertheless, the aforementioned powerful properties of the hypercube come at the cost of high VLSI complexity due to the increase in the number of communication ports and channels per PE (processing element) with an increase in the total number of PE’s. The high VLSI complexity of hypercube systems is undoubtedly their dominant drawback; it results in the construction of systems that contain either a large number of primitive PE’s or a small number of powerful PE’s. Therefore, low-dimensional k-ary n-cubes with lower VSLI complexity have recently drawn the attention of many designers of parallel computers. Alternative solutions reduce the hypercube’s VLSI complexity without jeopardizing its performance. Such an effort by Ziavras has resulted in the introduction of reduced hypercubes (RH’s). Taking advantage of existing high-performance routing techniques, such as wormhole routing, an RH is obtained by a uniform reduction in the number of edges for each hypercube node. An RH can also be viewed as several connected copies of the well-known cube-connected-cycles network. The objective here is to prove that parallel computers comprising RH interconnection networks are definitely good choices for all levels of image analysis. Since the exact requirements of high-level image analysis are difficult to identify, but it is believed that versatile interconnection networks, such as the hypercube, are suitable for relevant tasks, we investigate the problem of emulating hypercubes on RH’s. The ring (or linear array), the torus (or mesh), and the binary tree are the most frequently used topologies for the development of algorithms in low-level and intermediate-level image analysis. Thus, to prove the viability of the RH for the two lower levels of image analysis, we introduce techniques for embedding the aforementioned three topologies into RH’s. The results prove the suitability of RH’s for all levels of image analysis.

scholarly journals Conditional Fault-Diameter of Torus Networks

2005 ◽  
Vol 10 ◽  
pp. 51
Author(s):  
Abderezak Touzene ◽  
Khaled Day
Keyword(s):  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithms ◽  
Star Graph ◽  
Faulty Processor ◽  
Node Connectivity ◽  
Fault Diameter ◽  
Torus Networks ◽  
Vertex Disjoint

We obtain the conditional fault-diameter of the square torus interconnection network under the condition of forbidden faulty sets (i.e. assuming that each non-faulty processor has at least one non-faulty neighbor). We show that under this condition, the square torus, whose connectivity is 4, can tolerate up to 5 faulty nodes without becoming disconnected. The conditional node connectivity is, therefore, 6. We also show that the conditional fault-diameter of the square torus is equal to the fault-free diameter plus two. With this result the torus joins a group of interconnection networks (including the hypercube and the star-graph) whose conditional fault-diameter has been shown to be only two units over the fault-free diameter. Two fault-tolerant routing algorithms are discussed based on the proposed vertex disjoint paths construction.  

Energy-Efficient Optical Interconnects in Cloud Computing Infrastructures

2013 ◽  
pp. 463-478
Author(s):  
Christoforos Kachris ◽  
Ioannis Tomkos
Keyword(s):  
Cloud Computing ◽  
Power Consumption ◽  
Interconnection Networks ◽  
Optical Interconnects ◽  
High Performance ◽  
Interconnection Network ◽  
Research Literature ◽  
Optical Interconnection ◽  
High Bandwidth ◽  
Cloud Infrastructures

This chapter discusses the rise of optical interconnection networks in cloud computing infrastructures as a novel alternative to current networks based on commodity switches. Optical interconnects can significantly reduce the power consumption and meet the future network traffic requirements. Additionally, this chapter presents some of the most recent and promising optical interconnects architectures for high performance data centers that have appeared recently in the research literature. Furthermore, it presents a qualitative categorization of these schemes based on their main features such as performance, connectivity, and scalability, and discusses how these architectures could provide green cloud infrastructures with reduced power consumption. Finally, the chapter presents a case study of an optical interconnection network that is based on high-bandwidth optical OFDM links and shows the reduction of the energy consumption that it can achieve in a typical data center.

scholarly journals Low latency Path Aware XY-X Routing Algorithm for NoC Architectures

2018 ◽  
Vol 7 (2.7) ◽  
pp. 763
Author(s):  
Venkateswara Rao Musala ◽  
T V Rama Krishna
Keyword(s):  
High Performance ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Destination Node ◽  
Specific Information ◽  
Traffic Patterns ◽  
Traffic Conditions ◽  
Trade Offs ◽  
On Chip

Route specific information with the SoC needs a great deal of wiring, which increases the Resistance & Capacitance (RC) component of the system. Network on Chip (NoC) is utilized as the interface to address the problems in SoC, On-chip interconnection network in NoC has gained more consideration over steadfast wiring and buses, like lower latency, scalability and high performance. Present routing algorithms in NoC is suffered from load balancing at incarnation networks under non-uniform traffic conditions, causes increase the NoC trade-offs (latency and throughput). Adaptive routing is a technique to progress the load balance, but previous adaptive routing techniques used uniform traffic patterns to form the routing decisions. This paper proposes a new approach at non- uniform traffic patterns in channel state and path specific, Path Aware Routing (PAR XY-X) uses a timeout piggybacking for acknowledgement and load shedding to avoid congestion which choose optimistic path calculation unit to connect the destination node without glue logic decisions in routing. PAR XY-X outperforms the Normal XY routing by 20% and 33% with respect to Avg.latency and throughput.

ON THE COMPUTATIONAL COMPLEXITY OF ROUTING IN FAULTY K-ARY N-CUBES AND HYPERCUBES

2012 ◽  
Vol 22 (01) ◽  
pp. 1250003
Author(s):  
IAIN A. STEWART
Keyword(s):  
Computational Complexity ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Routing Algorithms ◽  
Source Node ◽  
Destination Node ◽  
Underlying Graph

We equate a routing algorithm in a (faulty) interconnection network whose underlying graph is a k-ary n-cube or a hypercube, that attempts to route a packet from a fixed source node to a fixed destination node, with the sub-digraph of (healthy) links potentially usable by this routing algorithm as it attempts to route the packet. This gives rise to a naturally defined problem, parameterized by this routing algorithm, relating to whether a packet can be routed from a given source node to a given destination node in one of our interconnection networks in which there are (possibly exponentially many) faulty links. We show that there exist such problems that are PSPACE-complete (all are solvable in PSPACE) but that there are (existing and popular) routing algorithms for which the computational complexity of the corresponding problem is significantly easier (yet still computationally intractable).

Fault-Tolerant Routing in Wormhole Meshes

2003 ◽  
Vol 04 (04) ◽  
pp. 463-495 ◽  
Author(s):  
Ming-Jer Tsai
Keyword(s):  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Fixed Number ◽  
One Dimension ◽  
Global Information ◽  
Unlimited Number ◽  
Fully Adaptive

In wormhole meshes, many a routing algorithm prevents a deadlock by enclosing unlimited number of faulty nodes with faulty blocks and dividing a physical interconnection network into a fixed number of virtual ones; none of them, however, is able to tolerate two faulty blocks with a distance of two, no less, in at least one dimension by use of only two virtual interconnection networks. To fill this gap, an adaptive and fault-tolerant routing algorithm is proposed. The algorithm is fully-adaptive until encountering a faulty block. It then detours the blocked message around the faulty block. Arranging the detours around faulty blocks attempts to prevent a deadlock. The proposed method has no need for global information.

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