A New Unicast Routing Algorithm for Hyper Hexa-Cell Interconnection Networks

2017 ◽  
Vol 8 (3) ◽  
pp. 45-57
Author(s):  
Jehad Ahmed Al-Sadi
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Optimal Path ◽  
Destination Node ◽  
Topological Properties ◽  
Unicast Routing ◽  
Cell Topology ◽  
Store And Forward ◽  
Point To Point

The Hyper Hexa-Cell topology; HHC for short; is a new interconnection network topology that has many attractive topological properties compared to other traditional topologies. There have been a number of studies in the literature on the HHC to explore the promising topological properties of this topology. Furthermore, other studies extend this topology by combining it with OTIS technology to produce a new version called OHHC. We have found that there is a lake of presenting any point to point routing algorithm for the HHC, although there were some efforts on building routing algorithms for the OHHC. To cover this shortage, this paper introduces a new unicast routing algorithm for the HHC. The new routing algorithm for the HHC uses store-and-forward technique which allows a message to be transmitted through a path from the source node to the destination node. In addition to presenting the routing algorithm, we present an example to explore the algorithm steps and also an enhancement on the routing algorithm to apply adaptively on the routing based on parameterized criteria. Finally, we present a theoretical theorem to prove that the algorithm routes any message from any source to any destination via an optimal path.

ON THE COMPUTATIONAL COMPLEXITY OF ROUTING IN FAULTY K-ARY N-CUBES AND HYPERCUBES

2012 ◽  
Vol 22 (01) ◽  
pp. 1250003
Author(s):  
IAIN A. STEWART
Keyword(s):  
Computational Complexity ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Routing Algorithms ◽  
Source Node ◽  
Destination Node ◽  
Underlying Graph

We equate a routing algorithm in a (faulty) interconnection network whose underlying graph is a k-ary n-cube or a hypercube, that attempts to route a packet from a fixed source node to a fixed destination node, with the sub-digraph of (healthy) links potentially usable by this routing algorithm as it attempts to route the packet. This gives rise to a naturally defined problem, parameterized by this routing algorithm, relating to whether a packet can be routed from a given source node to a given destination node in one of our interconnection networks in which there are (possibly exponentially many) faulty links. We show that there exist such problems that are PSPACE-complete (all are solvable in PSPACE) but that there are (existing and popular) routing algorithms for which the computational complexity of the corresponding problem is significantly easier (yet still computationally intractable).

scholarly journals Torus–Connected Cycles: A Simple and Scalable Topology for Interconnection Networks

2015 ◽  
Vol 25 (4) ◽  
pp. 723-735 ◽  
Author(s):  
Antoine Bossard ◽  
Keiichi Kaneko
Keyword(s):  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Hamiltonian Path ◽  
Small Diameter ◽  
Critical Parameters ◽  
Time Optimal ◽  
Point To Point ◽  
Torus Networks

Abstract Supercomputers are today made up of hundreds of thousands of nodes. The interconnection network is responsible for connecting all these nodes to each other. Different interconnection networks have been proposed; high performance topologies have been introduced as a replacement for the conventional topologies of recent decades. A high order, a low degree and a small diameter are the usual properties aimed for by such topologies. However, this is not sufficient to lead to actual hardware implementations. Network scalability and topology simplicity are two critical parameters, and they are two of the reasons why modern supercomputers are often based on torus interconnection networks (e.g., Fujitsu K, IBM Sequoia). In this paper we first describe a new topology, torus-connected cycles (TCCs), realizing a combination of a torus and a ring, thus retaining interesting properties of torus networks in addition to those of hierarchical interconnection networks (HINs). Then, we formally establish the diameter of a TCC, and deduce a point-to-point routing algorithm. Next, we propose routing algorithms solving the Hamiltonian cycle problem, and, in a two dimensional TCC, the Hamiltonian path one. Correctness and complexities are formally proved. The proposed algorithms are time-optimal.

THE CUBE-OF-RINGS INTERCONNECTION NETWORK

1998 ◽  
Vol 09 (01) ◽  
pp. 25-37 ◽  
Author(s):  
THOMAS J. CORTINA ◽  
ZHIWEI XU
Keyword(s):  
Graph Theory ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Parallel Computers ◽  
Closed Form Expression ◽  
Form Expression ◽  
Graph Theoretic ◽  
Basic Graph

We present a family of interconnection networks named the Cube-Of-Rings (COR) networks along with their basic graph-theoretic properties. Aspects of group graph theory are used to show the COR networks are symmetric and optimally fault tolerant. We present a closed-form expression of the diameter and optimal one-to-one routing algorithm for any member of the COR family. We also discuss the suitability of the COR networks as the interconnection network of scalable parallel computers.

BROADCASTING IN BUS INTERCONNECTION NETWORKS

2000 ◽  
Vol 01 (02) ◽  
pp. 73-94
Author(s):  
A. FERREIRA ◽  
A. GOLDMAN ◽  
S. W. SONG
Keyword(s):  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Parallel Architectures ◽  
Interprocessor Communication ◽  
Efficient Manner ◽  
Graph Theoretic ◽  
Communication Algorithms ◽  
Communication Links ◽  
Point To Point

In most distributed memory MIMD multiprocessors, processors are connected by a point-to-point interconnection network, usually modeled by a graph where processors are nodes and communication links are edges. Since interprocessor communication frequently constitutes serious bottlenecks, several architectures were proposed that enhance point-to-point topologies with the help of multiple bus systems so as to improve the communication efficiency. In this paper we study parallel architectures where the communication means are constituted solely by buses. These architectures can use the power of bus technologies, providing a way to interconnect much more processors in a simple and efficient manner. We present the hyperpath, hypergrid, hyperring, and hypertorus architectures, which are the bus-based versions of the well used point-to-point interconnection networks. Using (hyper) graph theoretic concepts to model inter-processor communication in such networks, we give optimal algorithms for broadcasting a message from one processor to all the others. For deriving high performance communication patterns we developed a new tool called simplification. The idea is to construct a graph, to be called representative graph, from the original hyper-topology, in such a way that it will become easy to describe and perform communication schemes to the former that will fit to the latter, because the simplification concept also allows us to partially use some already known communication algorithms for usual networks.

scholarly journals Topological Properties of Hierarchical Interconnection Networks: A Review and Comparison

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Mostafa Abd-El-Barr ◽  
Turki F. Al-Somani
Keyword(s):  
Packing Density ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Parallel Applications ◽  
Topological Properties ◽  
Remote Communication ◽  
Chip Area ◽  
Network Diameter ◽  
Link Cost

Hierarchical interconnection networks (HINs) provide a framework for designing networks with reduced link cost by taking advantage of the locality of communication that exists in parallel applications. HINs employ multiple levels. Lower-level networks provide local communication while higher-level networks facilitate remote communication. HINs provide fault tolerance in the presence of some faulty nodes and/or links. Existing HINs can be broadly classified into two classes. those that use nodes and/or links replication and those that use standby interface nodes. The first class includes Hierarchical Cubic Networks, Hierarchical Completely Connected Networks, and Triple-based Hierarchical Interconnection Networks. The second HINs class includes Modular Fault-Tolerant Hypercube Networks and Hierarchical Fault-Tolerant Interconnection Network. This paper presents a review and comparison of the topological properties of both classes of HINs. The topological properties considered are network degree, diameter, cost and packing density. The outcome of this study show among all HINs two networks that is, the Root-Folded Heawood (RFH) and the Flooded Heawood (FloH), belonging to the first HIN class provide the best network cost, defined as the product of network diameter and degree. The study also shows that HFCube(n,n)provide the best packing density, that is, the smallest chip area required for VLSI implementation.

Analysis the Performance of Interconnection Network Topology C2 Torus Based on Two Dimensional Torus

2018 ◽  
Vol 6 (6) ◽  
pp. 169 ◽  
Author(s):  
Prachi Chauhan ◽  
Manish Bhardwaj
Keyword(s):  
Network Topology ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Two Dimensional ◽  
Topological Properties ◽  
Interconnected Network ◽  
Dimensional Torus ◽  
Torus Network

Mesh and Torus are most popular interconnection topologies based on 2D-mesh.Comparison between Mesh and Torus will be considered and new interconnection topology will be proposed to provide better performance. The C2Mesh, is an enhanced mesh interconnected network. This paper enhances the torus network based on the theme of C2Mesh. Topological Properties of new network will be analyzed and implemented by simulation. The new routing Algorithm will be designed for new proposed network (C2Torus). This manuscript performs Comparison between C2Torus and C2Mesh.

Modified Gamma Network: Design and Reliability Evaluation

2019 ◽  
Vol 13 ◽  
Author(s):  
Shilpa Gupta ◽  
Gobind Lal Pahuja
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Network Reliability ◽  
Destination Node ◽  
Input Output ◽  
Switching Element ◽  
Node Pair ◽  
Multiple Processors ◽  
Output Stages

Background: VLSI technology advancements have resulted the requirements of high computational power, which can be achieved by implementing multiple processors in parallel. These multiple processors have to communicate with their memory modules by using Interconnection Networks (IN). Multistage Interconnection networks (MIN) are used as IN, as they provide efficient computing with low cost. Objective: the objective of the study is to introduce new reliable Gamma MIN named as a Modified Gamma Interconnection Network (MGIN), which provide reliability and fault-tolerance with less number of stages of Switching element only. Method: Switching Element (SE) of bigger size i.e. 2×3/3×2 has been employed at input/output stages inspite of 1×3/3×1 sized SE at input/output stages with reduction in one intermidiate stage. Fault tolerance has been introduced in the form of disjoint paths formed between each source-destnation node pair. Hence reliability has been improved. Results: Terminal, Broadcast and Network Reliability has been evaluated by using Reliability Block Diagrams for each source-destination node pair. The results have been shown, which depicts the higher reliability values for newly proposed network. The cost analysis shows that new MGIN is a cheaper network than other Gamma variants. Conclusion: MGIN has better reliability and Fault-tolerance than priviously proposed Gamma MIN.

scholarly journals Low latency Path Aware XY-X Routing Algorithm for NoC Architectures

2018 ◽  
Vol 7 (2.7) ◽  
pp. 763
Author(s):  
Venkateswara Rao Musala ◽  
T V Rama Krishna
Keyword(s):  
High Performance ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Destination Node ◽  
Specific Information ◽  
Traffic Patterns ◽  
Traffic Conditions ◽  
Trade Offs ◽  
On Chip

Route specific information with the SoC needs a great deal of wiring, which increases the Resistance & Capacitance (RC) component of the system. Network on Chip (NoC) is utilized as the interface to address the problems in SoC, On-chip interconnection network in NoC has gained more consideration over steadfast wiring and buses, like lower latency, scalability and high performance. Present routing algorithms in NoC is suffered from load balancing at incarnation networks under non-uniform traffic conditions, causes increase the NoC trade-offs (latency and throughput). Adaptive routing is a technique to progress the load balance, but previous adaptive routing techniques used uniform traffic patterns to form the routing decisions. This paper proposes a new approach at non- uniform traffic patterns in channel state and path specific, Path Aware Routing (PAR XY-X) uses a timeout piggybacking for acknowledgement and load shedding to avoid congestion which choose optimistic path calculation unit to connect the destination node without glue logic decisions in routing. PAR XY-X outperforms the Normal XY routing by 20% and 33% with respect to Avg.latency and throughput.

Fault-Tolerant Routing in Wormhole Meshes

2003 ◽  
Vol 04 (04) ◽  
pp. 463-495 ◽  
Author(s):  
Ming-Jer Tsai
Keyword(s):  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Fixed Number ◽  
One Dimension ◽  
Global Information ◽  
Unlimited Number ◽  
Fully Adaptive

In wormhole meshes, many a routing algorithm prevents a deadlock by enclosing unlimited number of faulty nodes with faulty blocks and dividing a physical interconnection network into a fixed number of virtual ones; none of them, however, is able to tolerate two faulty blocks with a distance of two, no less, in at least one dimension by use of only two virtual interconnection networks. To fill this gap, an adaptive and fault-tolerant routing algorithm is proposed. The algorithm is fully-adaptive until encountering a faulty block. It then detours the blocked message around the faulty block. Arranging the detours around faulty blocks attempts to prevent a deadlock. The proposed method has no need for global information.

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