Evolution of Adder and Subtractor Circuit Using Si3N4 Microring Resonator

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Ankur Saharia ◽  
Ashish Kumar Ghunawat ◽  
Manish Tiwari ◽  
Anton V. Bourdine ◽  
Vladimir A. Burdin ◽  
...  
Keyword(s):  
Numerical Simulations ◽  
Logic Gates ◽  
Full Adder ◽  
Microring Resonator ◽  
Microring Resonators ◽  
Basic Logic ◽  
Combinational Circuit ◽  
Half Adder ◽  
All Optical ◽  
Optical Processor

AbstractAll-optical processor capable of processing optical bits has been a long-standing goal of photonics. In this paper, we report the results obtained by numerical simulations regarding the designing of an all-optical combinational circuit of an adder and subtractor circuits based on Si3N4 microring resonators. The designs of combinational circuit like adders and subtractor based on the use of all-optical basic logic gates are discussed while presenting the numerically simulated results. Extinction ratios of 5.2 dB, 3.5 dB and 2.7 dB are obtained for the half adder, full adder and half subtractor, respectively.

scholarly journals Energy Efficient GDI Based Full Adders For Computing Applications

2020 ◽  
Vol 4 (6) ◽  
pp. 5-9
Author(s):  
Bilal N Md ◽  
Bhaskara Rao K ◽  
Mohan Das S
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Logic Gates ◽  
Full Adder ◽  
Low Power Consumption ◽  
Basic Logic ◽  
Power Delay Product ◽  
Full Swing

This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.

Design and Modeling of Polarization-Conversion Based all-Optical Basic Logic Gates in a Single Silicon Ring Resonator

Silicon ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 1279-1288 ◽  
Author(s):  
Gaurav Kumar Bharti ◽  
Madan Pal Singh ◽  
Jayanta Kumar Rakshit
Keyword(s):  
Ring Resonator ◽  
Logic Gates ◽  
Polarization Conversion ◽  
Basic Logic ◽  
All Optical
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