Integrated Optoelectronic Materials and Circuits for Optical Interconnects

1987 ◽  
Vol 108 ◽  
Author(s):  
L. D. Hutcheson
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Optoelectronic Devices ◽  
Critical Issue ◽  
Optoelectronic Materials ◽  
Input Output ◽  
Strong Case ◽  
On Chip

ABSTRACTConventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs Integrated Optoelectronic Circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected.

High-speed CMOS: Si light emitters for on-chip optical interconnects

2002 ◽  
Author(s):  
Amitabh Chatterjee ◽  
Bharat L. Bhuva ◽  
William C. Cieslik
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Light Emitters ◽  
On Chip

High-Speed and Stable Operation of Highly Unidirectional III-V/Silicon Microring Lasers for On-chip Optical Interconnects

CLEO: 2015 ◽  
2015 ◽  
Author(s):  
Kazuya Ohira ◽  
Hirotaka Uemura ◽  
Norio Iizuka ◽  
Haruhiko Yoshida ◽  
Hiroshi Uemura ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Stable Operation ◽  
On Chip

Toward high-speed, low-cost, on-chip silicon optical interconnects

SPIE Newsroom ◽  
2011 ◽  
Author(s):  
Xi Xiao ◽  
Haihua Xu ◽  
Yingtao Hu ◽  
Zhiyong Li ◽  
Yude Yu ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Low Cost ◽  
On Chip

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

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