Toward high-speed, low-cost, on-chip silicon optical interconnects

SPIE Newsroom ◽  
2011 ◽  
Author(s):  
Xi Xiao ◽  
Haihua Xu ◽  
Yingtao Hu ◽  
Zhiyong Li ◽  
Yude Yu ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Low Cost ◽  
On Chip

High-speed CMOS: Si light emitters for on-chip optical interconnects

2002 ◽  
Author(s):  
Amitabh Chatterjee ◽  
Bharat L. Bhuva ◽  
William C. Cieslik
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Light Emitters ◽  
On Chip

Bipolar device technology challenge and opportunity

1985 ◽  
Vol 63 (6) ◽  
pp. 683-692 ◽  
Author(s):  
H. D. Barber
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Chemical Vapor ◽  
Low Noise ◽  
Isolation Techniques ◽  
Propagation Delays ◽  
Technological Barriers ◽  
On Chip ◽  
Bipolar Device

Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

SENSING AND ACTUATING BIO-MATERIALS ON STANDARD CMOS SUBSTRATES

2013 ◽  
Vol 22 (02) ◽  
pp. 1250081 ◽  
Author(s):  
FAISAL T. ABU-NIMEH ◽  
FATHI M. SALEM
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Low Cost ◽  
Magnetic Bead ◽  
Column Switching ◽  
Parallel Operation ◽  
Coil Array ◽  
Lab On Chip ◽  
On Chip ◽  
Array Sensing

We present a low-cost, low-power, high efficiency, and portable integrated implementations of a lab-on-chip for magnetic molecular level sensing manipulation, and diagnosis. The design features an all-integrated programmable magnetic coil array for sensing and actuating small magnetic bead objects. The coil array is selectively and dynamically controlled using the smallest permissible vertical coil inductors in this technology. Each cell, composed of the coil and its logical control circuitry, can detect small objects in the order of 1 μm diameter as well as emit eight programmable magnetic field levels for manipulation. All array sensing and driving components are shared to reduce the overall imprint. They are tuned towards the 900 s MHz ISM band and incorporating high-speed serial row/column switching up to 40 MHz for seamless pseudo-parallel operation.

High-Speed and Stable Operation of Highly Unidirectional III-V/Silicon Microring Lasers for On-chip Optical Interconnects

CLEO: 2015 ◽  
2015 ◽  
Author(s):  
Kazuya Ohira ◽  
Hirotaka Uemura ◽  
Norio Iizuka ◽  
Haruhiko Yoshida ◽  
Hiroshi Uemura ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Stable Operation ◽  
On Chip

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Implementation of active interposer for high-speed and low-cost chip level optical interconnects

2003 ◽  
Vol 9 (2) ◽  
pp. 452-459 ◽  
Author(s):  
T. Mikawa ◽  
M. Kinoshita ◽  
K. Hiruma ◽  
T. Ishitsuka ◽  
M. Okabe ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Low Cost

scholarly journals A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4715
Author(s):  
Wei He ◽  
Jinguo Huang ◽  
Tengxiao Wang ◽  
Yingcheng Lin ◽  
Junxian He ◽  
...  
Keyword(s):  
Online Learning ◽  
High Speed ◽  
Low Cost ◽  
High Energy ◽  
Training Procedure ◽  
Vision Sensor ◽  
Clock Frequency ◽  
Dynamic Vision ◽  
Vlsi System ◽  
On Chip

This paper proposes a high-speed low-cost VLSI system capable of on-chip online learning for classifying address-event representation (AER) streams from dynamic vision sensor (DVS) retina chips. The proposed system executes a lightweight statistic algorithm based on simple binary features extracted from AER streams and a Random Ferns classifier to classify these features. The proposed system’s characteristics of multi-level pipelines and parallel processing circuits achieves a high throughput up to 1 spike event per clock cycle for AER data processing. Thanks to the nature of the lightweight algorithm, our hardware system is realized in a low-cost memory-centric paradigm. In addition, the system is capable of on-chip online learning to flexibly adapt to different in-situ application scenarios. The extra overheads for on-chip learning in terms of time and resource consumption are quite low, as the training procedure of the Random Ferns is quite simple, requiring few auxiliary learning circuits. An FPGA prototype of the proposed VLSI system was implemented with 9.5~96.7% memory consumption and <11% computational and logic resources on a Xilinx Zynq-7045 chip platform. It was running at a clock frequency of 100 MHz and achieved a peak processing throughput up to 100 Meps (Mega events per second), with an estimated power consumption of 690 mW leading to a high energy efficiency of 145 Meps/W or 145 event/μJ. We tested the prototype system on MNIST-DVS, Poker-DVS, and Posture-DVS datasets, and obtained classification accuracies of 77.9%, 99.4% and 99.3%, respectively. Compared to prior works, our VLSI system achieves higher processing speeds, higher computing efficiency, comparable accuracy, and lower resource costs.

Integrated Optoelectronic Materials and Circuits for Optical Interconnects

1987 ◽  
Vol 108 ◽  
Author(s):  
L. D. Hutcheson
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Optoelectronic Devices ◽  
Critical Issue ◽  
Optoelectronic Materials ◽  
Input Output ◽  
Strong Case ◽  
On Chip

ABSTRACTConventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs Integrated Optoelectronic Circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected.

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