Effects of Silicon Ion Implantation upon Thin Gate Oxide Integrity

1992 ◽  
Vol 262 ◽  
Author(s):  
G. -S. Lee ◽  
J. -G. Park ◽  
S. -P. Choi ◽  
C. -H. Shin ◽  
Y. -B. Sun ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Surface Region ◽  
Gate Oxide ◽  
Near Surface ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide ◽  
Si Ion Implantation ◽  
Gate Oxide Integrity

ABSTRACTIn this study, using oxide breakdown voltage and time-dependent-dielectric breakdown measurements, thermal wave modulated reflectance and chemical etching/optical microscopy, we investigated effects of Si ion implantation upon formation of D-defects and thin gate oxide integrity. Our data show that addition of Si ion implantation with a dose of up to 1013 ions/cm2 improves oxide integrity if the implantation is done at a certain step just before sacrificial oxidation in the Mb DRAM process. However, no improvement in oxide integrity is observed when the same implantation is done on the virgin wafer surfaces at the start of the same Mb DRAM process. We discuss our hypothesis that the improvement in oxide integrity is due to a reduction in the D-defect density in the near-surface region of the wafer.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

High Temperature Gate Voltage Step-by-Step Test to Assess Reliability Differences in 1200 V SiC MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 1033-1044
Author(s):  
Elena Mengotti ◽  
Enea Bianda ◽  
Stephan Wirths ◽  
David Baumann ◽  
Jason Bettega ◽  
...  
Keyword(s):  
Gate Voltage ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Imperfect Interface ◽  
Step Test ◽  
Limiting Factor ◽  
Voltage Step ◽  
Good Reliability ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide

In this paper, robustness and reliability differences related to the performance of the gate oxide of commercially-available 1200 V-rated planar and trench SiC MOSFETs have been investigated. Due to a thin gate oxide in SiC MOSFETs and to a naturally imperfect interface of the oxide layer (SiO2) with the SiC material, its quality and reliability become very important and could be a limiting factor of the SiC technology when compared to the Si one. A dedicated gate oxide step-by-step (VG SbS) tester has been prepared during which the gate voltage is varied with different profiles. Results of Fowler-Nordheim (FN), Time Dependent Dielectric Breakdown (TDDB) and three test runs of the VG SbS are presented in this paper. Both technologies show good reliability figures to allow the use in the application. Trench technology shows higher robustness limits whereas the extrapolated reliability at the rated gate voltage is superior for the planar one.

Si Ion Implantation for Secondary Defect Reduction in Simox Material

1993 ◽  
Vol 316 ◽  
Author(s):  
S.L. Ellingboe ◽  
M.C. Ridgway
Keyword(s):  
Ion Implantation ◽  
Surface Region ◽  
Defect Reduction ◽  
Near Surface ◽  
Secondary Defect ◽  
Si Ion Implantation

ABSTRACTA novel methodology for altering the amount and/or nature of post-anneal disorder in SIMOX substrates has been investigated. A pre-anneal, secondary Si-ion implant (with an ion range less than that of the primary O-ion implant) is shown to effectively getter Si interstitials to the near-surface region during annealing. As a consequence, post-anneal disorder at the front. Si/SiO2 interface is significantly reduced. Alternatively, a Si-ion implant with an ion range greater than that of the O-ion implant can alter the post-anneal disorder at the back Si/SiO2 interface.

The Effects of Ion Implantation on the Surface Features of Inconel 600

1985 ◽  
Vol 43 ◽  
pp. 288-289
Author(s):  
John D. Rubio
Keyword(s):  
Grain Boundary ◽  
Ion Implantation ◽  
Nuclear Power ◽  
Power Plants ◽  
Surface Region ◽  
Selective Dissolution ◽  
Boundary Region ◽  
Near Surface ◽  
Inconel 600 ◽  
Steam Generator Tubing

The degradation of steam generator tubing at nuclear power plants has become an important problem for the electric utilities generating nuclear power. The material used for the tubing, Inconel 600, has been found to be succeptible to intergranular attack (IGA). IGA is the selective dissolution of material along its grain boundaries. The author believes that the sensitivity of Inconel 600 to IGA can be minimized by homogenizing the near-surface region using ion implantation. The collisions between the implanted ions and the atoms in the grain boundary region would displace the atoms and thus effectively smear the grain boundary.To determine the validity of this hypothesis, an Inconel 600 sample was implanted with 100kV N2+ ions to a dose of 1x1016 ions/cm2 and electrolytically etched in a 5% Nital solution at 5V for 20 seconds. The etched sample was then examined using a JEOL JSM25S scanning electron microscope.

Study of Time Dependent Dielectric Breakdown Distribution in Ultrathin Gate Oxide

2007 ◽  
Vol 46 (No. 28) ◽  
pp. L691-L692 ◽  
Author(s):  
Takashi Miyakawa ◽  
Tsutomu Ichiki ◽  
Junichi Mitsuhashi ◽  
Kazutoshi Miyamoto ◽  
Tetsuo Tada ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Time Dependent Dielectric Breakdown
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