Improved Reliability With a New Plasma Nh3 Process for 0.35μιη P+ Poly-Gate Nitrided Oxide P-Mosfet's

1996 ◽  
Vol 446 ◽  
Author(s):  
A. Bravaix ◽  
D. Vuillaume ◽  
D. Goguenheim ◽  
V. Lasserre ◽  
A. Straboni ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Barrier Properties ◽  
Oxide Thickness ◽  
Lower Amount ◽  
Interface Traps ◽  
Gate Oxides ◽  
Hot Carrier ◽  
Gate Oxide Thickness ◽  
Donor Type ◽  
Main Influence

AbstractThe electrical properties and the hot-carrier reliability of P+ poly-gate P-MOSFET's are investigated for advanced 0.35 μπι LDD CMOS technologies. It is shown that surface-channel p-devices with an optimized plasma NH3 nitrided gate-oxide have good barrier properties and electrical performances which lead to a higher hot-carrier immunity in 8nm thick nitrided gate-oxides than in pure oxides using DC and AC experiments. The AC stressing shows that reducing the gate-oxide thickness leads to a larger influence of electron detrapping inducing a stronger influence of donor type interface traps than the usual build-up of negative charges. These distinct degradation mechanisms are less significant in nitrided oxide p-MOSFET's due to the lower lateral electric field leading to a lower amount of trapped charges which are quickly suppressed during subsequent detrapping phases leaving the main influence of the interface traps.

Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's

1995 ◽  
Vol 42 (1) ◽  
pp. 116-122 ◽  
Author(s):  
B.S. Doyle ◽  
K.R. Mistry ◽  
Cheng-Liang Huang
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Hot Carrier ◽  
Gate Oxide Thickness ◽  
Hot Carrier Effects

scholarly journals HRTEM Image Simulations for the Study of Ultrathin Gate Oxides

2002 ◽  
Vol 8 (5) ◽  
pp. 412-421 ◽  
Author(s):  
Seth T. Taylor ◽  
John Mardinly ◽  
Michael A. O'Keefe
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Structural Defects ◽  
Objective Lens ◽  
Specimen Thickness ◽  
Hrtem Image ◽  
Gate Oxides ◽  
Gate Oxide Thickness ◽  
Simulated Images ◽  
Image Simulations

We have performed high resolution transmission electron microscope (HRTEM) image simulations to qualitatively assess the visibility of various structural defects in ultrathin gate oxides of MOSFET devices, and to quantitatively examine the accuracy of HRTEM in performing gate oxide metrology. Structural models contained crystalline defects embedded in an amorphous 16-Å-thick gate oxide. Simulated images were calculated for structures viewed in cross section. Defect visibility was assessed as a function of specimen thickness and defect morphology, composition, size, and orientation. Defect morphologies included asperities lying on the substrate surface, as well as “bridging” defects connecting the substrate to the gate electrode. Measurements of gate oxide thickness extracted from simulated images were compared to actual dimensions in the model structure to assess TEM accuracy for metrology. The effects of specimen tilt, specimen thickness, objective lens defocus, and coefficient of spherical aberration (Cs) on measurement accuracy were explored for nominal 10-Å gate oxide thickness. Results from this work suggest that accurate metrology of ultrathin gate oxides (i.e., limited to several percent error) is feasible on a consistent basis only by using a Cs-corrected microscope. However, fundamental limitations remain for characterizing defects in gate oxides using HRTEM, even with the new generation of Cs-corrected microscopes.

Sign in / Sign up

Export Citation Format

Share Document