A Comparison of Mos Devices with In-Situ Boron Doped Polysilicon and Poly Sige Gates Deposited in an Rtcvd System Using S12H6 and B2H6 Gas Mixture

1998 ◽  
Vol 525 ◽  
Author(s):  
M. R. Mirabedini ◽  
V. Z-Q Li ◽  
A. R. Acker ◽  
R. T. Kuehn ◽  
D. Venables ◽  
...  

ABSTRACTIn this work, in-situ doped polysilicon and poly-SiGe films have been used as the gate material for the fabrication of MOS devices to evaluate their respective performances. These films were deposited in an RTCVD system using a Si2H6 and GeH4 gas mixture. MOS capacitors with 45 Å thick gate oxides and polysilicon/poly-SiGe gates were subjected to different anneals to study boron penetration. SIMS analysis and flat band voltage measurements showed much lower boron penetration for devices with poly-SiGe gates than for devices with polysilicon gates. In addition, C-V measurements showed no poly depletion effects for poly-SiGe gates while polysilicon gates had a depletion effect of about 8%. A comparison of resistivities of these films showed a low resistivity of 1 mΩ-cm for poly-SiGe films versus 3 mΩ-cm for polysilicon films after an anneal at 950 °C for 30 seconds.

1998 ◽  
Vol 524 ◽  
Author(s):  
L.-S. Hsu ◽  
J. D. Denlinger ◽  
J. W. Allen

ABSTRACTIn this work, in-situ doped polysilicon and poly-SiGe films have been used as the gate material for the fabrication of MOS devices to evaluate their respective performances. These films were deposited in an RTCVD system using a Si2H6 and GeH4 gas mixture. MOS capacitors with 45 Å thick gate oxides and polysilicon/poly-SiGe gates were subjected to different anneals to study boron penetration. SIMS analysis and flat band voltage measurements showed much lower boron penetration for devices with poly-SiGe gates than for devices with polysilicon gates. In addition, C-V measurements showed no poly depletion effects for poly-SiGe gates while polysilicon gates had a depletion effect of about 8%. A comparison of resistivities of these films showed a low resistivity of 1 mΩ-cm for poly-SiGe films versus 3 mΩ-cm for polysilicon films after an anneal at 950 °C for 30 seconds.


2007 ◽  
Vol 996 ◽  
Author(s):  
Takuya Sugawara ◽  
Raghavasimhan Sreenivasan ◽  
Yasuhiro Oshima ◽  
Paul C. McIntyre

AbstractGermanium and hafnium-dioxide (HfO2) stack structures' physical and electrical properties were studied based on the comparison of germanium and silicon based metal-oxide-semiconductor (MOS) capacitors' electrical properties. In germanium MOS capacitor with oxide/oxynitride interface layer, larger negative flat-band-voltage (Vfb) shift compared with silicon based MOS capacitors was observed. Secondary ion mass spectrum (SIMS) characteristics of HfO2-germanium stack structure with germanium oxynitride (GeON) interfacial layer showed germanium out diffusion into HfO2. These results indicate that the germanium out diffusion into HfO2 would be the origin of the germanium originated negative Vfb shift. Using Ta3N5 layer as a germanium passivation layer, reduced Vfb shift and negligible hysteresis were observed. These results suggest that the selection of passivation layer strongly influences the electrical properties of germanium based MOS devices.


1998 ◽  
Vol 525 ◽  
Author(s):  
A. Srivastava ◽  
H. H. Heinisch ◽  
E. Vogel ◽  
C. Parker ◽  
C. M. Osburn ◽  
...  

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.


1995 ◽  
Vol 403 ◽  
Author(s):  
H. Kahn ◽  
S. Stemmer ◽  
R. L. Mullen ◽  
M. A. Huff ◽  
A. H. Heuer

AbstractPolycrystalline silicon is the most widely used structural material for surface micromachined microelectromechanical systems (MEMS). There are many advantages to using thick polysilicon films; however, due to process equipment limitations, these devices are typically fabricated from polysilicon films less than 3 μm thick. In this work, microelectromechanical test structures were designed and processed from thick (up to 10 μm) in situ boron-doped polysilicon films. The elastic modulus of these films was about 150 GPa, independent of film thickness. The thermal oxidation of the polysilicon induced a compressive stress into the top surface of the films, which was detected as a residual stress in the polysilicon after the device fabrication was complete.


1998 ◽  
Vol 335 (1-2) ◽  
pp. 70-79 ◽  
Author(s):  
M. Boukezzata ◽  
B. Birouk ◽  
D. Bielle-Daspet

2001 ◽  
Vol 669 ◽  
Author(s):  
E. J. Stewart ◽  
M. S. Carroll ◽  
J.C. Sturm

ABSTRACTPreviously, it has been reported that PMOS capacitors with heavily boron-doped polycrystalline SiGeC gates are less susceptible to boron penetration than those with poly Si gates [1]. Boron appears to accumulate in the poly SiGeC layers during anneals, reducing boron outdiffusion from the gate despite high boron levels in the poly SiGeC at the gate/oxide interface. In this abstract, we report clear evidence of strong boron segregation to polycrystalline SiGeC layers from poly Si, with boron concentration in poly SiGeC (Ge=25%, C=1.5%) increasing to four times that of adjacent poly Si layers. A separate experiment confirms that this result is not due to any SIMS artifacts. Electrical measurements of heavily in-situ doped single layer samples show that the conductivity of poly SiGeC is similar to poly Si and remains roughly constant with annealing at 800°C. However, in a two-layer sample where the poly SiGeC is initially lightly doped and subsequently heavily doped by diffusion by from an adjacent poly Si layer, conductivity appears lower than in poly Si.


2001 ◽  
Vol 670 ◽  
Author(s):  
S.-K. Kang ◽  
J. J. Kim ◽  
D.-H. Ko ◽  
T. H. Ahn ◽  
I. S. Yeo ◽  
...  

ABSTRACTWe investigated the electrical characteristics of the MOSCAP structures with W/WNx/poly Si1−xGex gates stack using C-V and I-V. The low frequency C-V measurements demonstrated that the flat band voltage of the W/WNx /poly Si0.4Ge0.6 stack was lower than that of W/ WNx /poly Si0.2Ge0.8 stack by 0.3V, and showed less gate-poly-depletion-effect than that of W/ WNx /poly- Si0.2Ge0.8 gates due to the increase of dopant activation rate with the increase of Ge content in the poly Si1−xGex films. As Ge content in poly Si1−xGex increased, the leakage current level increased a little due to the increase of direct tunneling and QBD became higher due to the lower boron penetration.


2018 ◽  
Vol 924 ◽  
pp. 449-452 ◽  
Author(s):  
Yi Fan Jia ◽  
Hong Liang Lv ◽  
Xiao Yan Tang ◽  
Qing Wen Song ◽  
Yi Men Zhang ◽  
...  

The characteristics of near interface electron and hole traps in n-type 4H-SiC MOS capacitors with and without nitric oxide (NO) passivation have been systematically investigated. The hysteresis of the bidirectional capacitance-voltage (C-V) and the shift of flat band voltage (Vfb) caused by bias stress (BS) with and without ultraviolet light (UVL) irradiation are used for studying the influence of near interface electron traps (NIETs) and near interface hole traps (NIHTs). Compared with Ar annealed process, NO passivation can effectively reduce the density of NIETs, but induce excess NIHTs in the SiC MOS devices. What’s worse is that part of the trapped hole cannot be released easily from the NIHTs in the NO annealed sample, which may act as the positive fixed charge and induce the negative shift of threshold voltage.


1999 ◽  
Vol 605 ◽  
Author(s):  
J. J. McMahon ◽  
J. J. McMahon ◽  
J. M. Melzak ◽  
C. A. Zorman ◽  
J. Chung ◽  
...  

AbstractIn an effort to develop thick, p-type polycrystalline silicon (polysilicon) films for microelectromechanical systems (MEMS) applications, in-situ boron-doped polysilicon films were deposited by a single-step APCVD process at susceptor temperatures ranging from 700°C to 955°C. The process produces boron-doped films at a deposition rate of 73 nm/min at 955°C. Spreading resistance measurements show that the boron doping level is constant at 2 × 1019 /cm3 throughout the thickness of the films. Doped films deposited at the low temperatures exhibit compressive stress as high as 666 Mpa; however films deposited at 955°C exhibited stress as low as 130 MPa. TEM and XRD show that the microstructure strongly depends on the deposition conditions. Surface micromachined, singly clamped cantilevers and strain gauges were successfully fabricated and used to characterize the residual stress of 5.0 µm-thick doped films deposited at a susceptor temperature of 955°C.


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