FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance

Due to the exponential increase of electronic devices that are connected to the Internet, the amount of data that they produce have grown to the same extent. In order to face the processing of these data, the use of some automatic learning algorithms, also known as Machine Learning, has become widespread. The most popular is the one known as neural networks. These algorithms need a great deal of resources to compute all their operations, and because of that, they have been traditionally implemented in application specific integrated circuits. However, recently there have been a boom in implementations in field programmable gate arrays, also known as FPGAs. These allow greater parallelism in the implementation of the algorithms. Field Programmable Gate Arrays (FPGA) implementation based feature extraction method is proposed in this paper. This particular application is handwritten offline digit recognition. The classification depends on simple 2 layer MultiLayer Perceptron (MLP). The particular feature extraction approach is suitable for execution of FPGA because it is utilized with subtraction and addition operations. From Standard database handwritten digit images of normalized 40×40 pixel the features are extracted by the proposed method. It has been discovered by experiential outcomes that 85% accuracy is achieved by proposed system. Overall, as compared to other systems, it is less complex, more accurate and simple. Further this project explains IEE-754 format single precision floating point MAC unit’s FPGA implementation which is utilized for feeding the neurons weighted inputs in artificial neural networks. Data representation range is improved by floating point numbers utilization to a higher number from smaller number that is highly suggested for Artificial Neuron Network. The code is developed in HDL, simulated and synthesis results are extracted using Xilinx synthesis tools .In order to validate its computational accuracy of the FFT, an MATLAB validation script is used to verify the output of HDL with standard reference model.

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Power Consumption Aware Machine Learning Attack for Feed-Forward Arbiter PUF

Computer and Information Science - Studies in Computational Intelligence ◽

10.1007/978-3-319-98693-7_4 ◽

2018 ◽

pp. 49-62 ◽

Cited By ~ 1

Author(s):

Yusuke Nozaki ◽

Masaya Yoshikawa

Keyword(s):

Machine Learning ◽

Power Consumption ◽

Feed Forward ◽

Arbiter Puf

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Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA

Electronics ◽

10.3390/electronics9050815 ◽

2020 ◽

Vol 9 (5) ◽

pp. 815 ◽

Cited By ~ 1

Author(s):

Yijun Cui ◽

Chongyan Gu ◽

Qingqing Ma ◽

Yue Fang ◽

Chenghua Wang ◽

...

Keyword(s):

Machine Learning ◽

Mathematical Model ◽

Sample Size ◽

High Resistance ◽

Hardware Implementation ◽

Machine Learning Algorithms ◽

Experimental Results ◽

Large Sample Size ◽

Prediction Rate ◽

Arbiter Puf

Physical unclonable function (PUF) is a primary hardware security primitive that is suitable for lightweight applications. However, it is found to be vulnerable to modeling attacks using machine learning algorithms. In this paper, multiplexer (MUX)-based Multi-PUF (MMPUF) design is proposed to thwart modeling attacks. The proposed design uses a weak PUF to obfuscate the challenge of a strong PUF. A mathematical model of the proposed design is presented and analyzed. The three most widely used modeling attack techniques are used to evaluate the resistance of the proposed design. Experimental results show that the proposed MMPUF design is more resistant to the machine learning attack than the previously proposed XOR-based Multi-PUF (XMPUF) design. For a large sample size, the prediction rate of the proposed MMPUF is less than the conventional Arbiter PUF (APUF). Compared with existing attack-resistant PUF designs, the proposed MMPUF design demonstrates high resistance. To verify the proposed design, a hardware implementation on Xilinx 7 Series FPGAs is presented. The hardware experimental results show that the proposed MMPUF designs present good results of uniqueness and reliability.

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Configurations of memristor-based APUF for improved performance

Bulletin of Electrical Engineering and Informatics ◽

10.11591/eei.v8i1.1401 ◽

2019 ◽

Vol 8 (1) ◽

pp. 74-82

Author(s):

Julius Han Loong Teo ◽

Noor Alia Noor Hashim ◽

Azrul Ghazali ◽

Fazrena Azlee Hamid

Keyword(s):

Machine Learning ◽

Support Vector Machine ◽

Monte Carlo ◽

Monte Carlo Simulations ◽

Learning Algorithms ◽

Machine Learning Algorithms ◽

Support Vector ◽

Arbiter Puf ◽

Improved Performance ◽

The Ideal

The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance.

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