Adaptive filters have wide range of applications in areas such as echo or interference cancellation, prediction and system identification. Due to high computational complexity of adaptive filters, their hardware implementation is not an easy task. However, it becomes essential in many cases where real-time execution is needed. This paper presents the design and hardware implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. To ensure an area efficient implementation, a novel structure is being proposed. The proposed structure eliminates the requirement of extra registers for storage of delayed inputs thereby reducing the silicon area. The structure is compared with direct-form and transposed-form structures by adapting the filter coefficients using four different variants of the least means square (LMS) algorithm. Subsequently, the filters are implemented on three different field programmable gate arrays (FPGAs) viz. Spartan 6, Virtex 6 and Virtex 7 to find out the best device family that can be used to implement an Adaptive noise canceller (ANC) by comparing speed, power and area utilization. The synthesis results clearly reveal that ANC designed using the proposed structure has resulted in a reduction in silicon area without incurring any significant overhead in terms of power or delay.
Adaptive method to predict and track unknown system behaviors using RLS and LMS algorithms
