scholarly journals Kajian Implementasi Field Programmable Gate Array untuk Rencana Modernisasi Sistem Proteksi Reaktor

2020 ◽  
Vol 22 (2) ◽  
pp. 119
Author(s):  
Restu Maerani ◽  
Tulis Jojok Suryono ◽  
Sigit Santoso ◽  
Muhammad Subekti

Penggunaan Field Programmable Gate Array (FPGA) pada reaktor nuklir sudah dilakukan sejak 2016, terutama diaplikasikan pada perangkat Sistem Instrumentasi dan Kendali (SIK). FPGA sebelumnya sudah diujikan pada rancangan Sistem Proteksi Reaktor (SPR) dan Engineered Safety Feature – Component Control System (ESF-CCS) reaktor daya tipe APR1400. Dengan adanya rencana peremajaan SIK reaktor serbaguna G.A. Siwabessy (RSG-GAS) pada bagian SPR, diharapkan sistem berbasis FPGA juga dapat diimplementasikan pada reaktor riset. Dengan pertimbangan nilai ekonomi, keamanan dan juga keandalannya, FPGA yang berbasis perangkat keras dinilai akan lebih aman dari serangan jaringan, lebih murah dari Programmable Logic Controller (PLC) yang berbasis perangkat lunak dan proses verifikasi dan validasinya yang lebih sederhana. Untuk menjamin berlangsungnya performa SPR RSG-GAS, proses digitalisasi perangkat kendali tidak dapat dihindari dan sebaiknya dilakukan. Penelitian ini membahas siklus perancangan berbasis FPGA yang diawali dengan mengkaji dokumen panduan terkait sistem yang penting untuk keselamatan terutama yang berbasis FPGA agar dapat mengacu kepada persyaratan, baik untuk perancangan perangkat keras maupun perangkat lunak, proses reverse engineering hingga proses validasi. Hasil dari penelitian ini bertujuan agar pada proses desain dalam upaya peremajaan SPR RSG-GAS dapat mengikuti metode yang telah disyaratkan terkait perancangan SIK berbasis FPGA untuk reaktor riset, sehingga dapat mempermudah proses perolehan ijin dari badan pengawas tenaga nuklir untuk dapat dilakukan penggantian desain SPR berbasis FPGA.

2006 ◽  
Vol 94 (2) ◽  
pp. 165-177 ◽  
Author(s):  
Rodrigo Castañeda-Miranda ◽  
Eusebio Ventura-Ramos ◽  
Rebeca del Rocío Peniche-Vera ◽  
Gilberto Herrera-Ruiz

Author(s):  
Dhafer J. Almakhles ◽  
Akshya Swain ◽  
Hou Yuefeng

<p>In this paper, a Sigma-Delta Quantizer (∑∆-Q) based Proportional and Integral control is proposed for a wireless power transfer control system, namely inductive power transfer system. The proposed control topology employs ∑∆-Qs to convert the conventional signals (analog/digital signals) into bitsreatm signals (1-bit per sample time). Considering the oversampling feature of ∑∆-Q, field programmable gate array is utilized in the implementation of the control system. To evaluate the effectiveness of the presented control topology, it is compared with an inductive power transfer control system using the conventional proportional and integral controller. For the sake of simplicity, the comparison is carried out using hardware in Loop. Both control systems exhibit almost identical responses. However, the bitstream feature of the proposed PI controller significantly helps in reducing the hardware resources (logic elements) in field programmable gate array. In addition, less wire routing and computational complexity is achieved due to absence of multipliers.</p>


2013 ◽  
Vol 418 ◽  
pp. 012059 ◽  
Author(s):  
Zi Sheng Zhang ◽  
Chang Xie ◽  
Yan Qing Xiong ◽  
Zhi Qiang Liu ◽  
Qing Li

Author(s):  
Francisco Bilendo ◽  
Sheng Shouzhao

Abstract— Flight Control System is an integrated avionics system equipped with the minimum required components for an autonomous flight. This paper focuses on the Hardware Design of the Flight Control System and presents specific details of the components and its interface. The system architecture is based on Field Programmable Gate Array and Digital Signal Processor. Employing these two processors in the flight control system would improve the Flight Control System performance in terms of fast sequential processing of high-level control algorithms. In addition to Field Programmable Gate Array and Digital Signal Processor, the flight control computer system will also make use of Global Positioning System and Micro Electro Mechanical System sensors. The project will be implemented using Altera’s System On Programmable Chip builder, currently known as Qsys – Platform Designer implemented in Quartus-II. The system employs Nios-II processor which is 32-bit soft-core embedded-processor architecture designed especially for the Altera’s family of Field Programmable Gate Array. From conceptualization to final design, this paper presents the functionality of the different modulus and complex interfaces employed in this Flight Control System.


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