An Effective on-Chip Network Topology for Network on Chip (Noc) Trade-Offs

Network-on-Chip (NoC) is a strong candidate for scalable interconnect design of Multi-Processor System-on-Chip (MPSoC). Software tasks of MPSoC require a certain protocol to communicate with each other. In NoC such a communication protocol should be handled at Network Interface and/or Processor Element level and it is expected that different protocols show their trade-offs. In consideration of the above, we employed two types of basic protocol and investigated their performance impact. The contribution of this work is to quantitatively evaluate effectiveness of using separate communication protocols depending on the task structure.

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A Topology Optimization Method of Application-Specific Network-on-Chip

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.457-458.905 ◽

2012 ◽

Vol 457-458 ◽

pp. 905-912

Author(s):

Guo Ming Lai ◽

Xiao La Lin

Keyword(s):

Network Topology ◽

Optimization Method ◽

Network On Chip ◽

Optimal Topology ◽

Single Chip ◽

Communication Problems ◽

On Chip ◽

Application Specific ◽

Total Network ◽

Topology Optimization Method

Future high-end System-on-chips (SoCs) will be consisted of hundreds of cores integrated on a single chip. On-chip communication becomes the major performance bottleneck of SoCs. Network-on-Chip (NoCs) have become as the most prominent solution to on-chip communication problems. Network topology which affects the total network conformance is basic of network related researches. The objective of topology synthesis is to minimize the power consumption and router resources while satisfying bandwidth constraints. In this paper, we present a two-level genetic-algorithm (GA) based technique to synthesize application-specific NoC topology. Comparing to an existing three-level GA, experiments show that our technique saves 1.8% energy while saving great runtimes of 97.79%. Our technique generates approximate optimal topology less than one minute.

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Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases

First International Symposium on Networks-on-Chip (NOCS'07) ◽

10.1109/nocs.2007.45 ◽

2007 ◽

Cited By ~ 38

Author(s):

Andreas Hansson ◽

Kees Goossens

Keyword(s):

Network On Chip ◽

Use Cases ◽

Multiple Use ◽

Trade Offs ◽

On Chip

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Improved XFBT: A Low-Power Topology of Network-on-Chip

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.989-994.4865 ◽

2014 ◽

Vol 989-994 ◽

pp. 4865-4868

Author(s):

Hong Bing Chen ◽

Chao Li

Keyword(s):

Power Consumption ◽

Low Power ◽

Network Topology ◽

Network On Chip ◽

Simulation Program ◽

On Chip

The article discusses the issues related to the on-chip network topology, analyzes the XBFT topology, improves its structure in power consumption. Authors designed a simulation program that by analyzing the topology routing hops to roughly determine the power consumption of routing topology and for the preparation of modified XBFT roughly determine the topology of the routing topology by analyzing the power consumption topology routing hops the simulation program, Finally, the results from the running of 6 simulation program that extracted and these results were analyzed. The result shows that the improved topology saved about 20% of the number of routing hops.

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