scholarly journals A Modified Shuffling Method to Reduce Decoding Complexity of QC-LDPC Codes

2020 ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Belief Propagation ◽  
Iterative Algorithms ◽  
Ldpc Codes ◽  
Parallel Architectures ◽  
Parity Check ◽  
Low Snr ◽  
Memory Overhead ◽  
Field Programmable ◽  
On Chip ◽  
The Right

Abstract Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.

scholarly journals Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling

2021 ◽  
Vol 2021 (1) ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Belief Propagation ◽  
Parallel Architecture ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Parity Check ◽  
Codeword Length ◽  
Check Matrix ◽  
Field Programmable ◽  
On Chip ◽  
The Right

AbstractLayered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of $$E_b/N_0$$ E b / N 0 until the BER of 1e−6.

Hybrid Decoding Algorithm for LDPC Codes with Circles

2011 ◽  
Vol 271-273 ◽  
pp. 258-263
Author(s):  
Li Shuang Hu ◽  
Ming Shan Liu ◽  
Yuan Zhou ◽  
Yang Sun
Keyword(s):  
Error Rate ◽  
Belief Propagation ◽  
Additive White Gaussian Noise ◽  
Ldpc Codes ◽  
Error Correcting Codes ◽  
Parity Check ◽  
Likelihood Ratios ◽  
Decoding Algorithms ◽  
Variable Node ◽  
Check Node

At present, Low-Density Parity-Check (LDPC) codes widely used in many fields of communications have the best performance of all the Error Correcting Codes (ECC). This paper mainly studies the decoding algorithms of LDPC. It proposes an improved algorithm which is named Check-Variable nodes Hybrid(CVH) algorithm on the basis of the existing algorithms. The CVH algorithm can reduce the computational complexity during the check-node update while overcome with the correlation between the variable-node news in a code with circles. As well as, comparing with the original algorithms the performance of the new one saves 0.1 and 0.3 dB than Log-likelihood Ratios (LLR) Belief Propagation (BP) and BP - based algorithms under Additive White Gaussian Noise (AWGN) channel when the Bit Error Rate (BER) falls to through the simulation. This point shows that this algorithm can increase the decoding performance and reduce the error rate effectively.

LDPC Codes with the Layered LLR-BP Algorithm for 3GPP

2013 ◽  
Vol 462-463 ◽  
pp. 720-723
Author(s):  
Miao Miao Li ◽  
Jian Ping Li ◽  
Chao Shi Cai
Keyword(s):  
Belief Propagation ◽  
Ldpc Codes ◽  
Bp Algorithm ◽  
Parity Check ◽  
Computation Complexity ◽  
Decoding Algorithm ◽  
Absolute Value ◽  
Low Density Parity Check ◽  
Variable Node ◽  
Log Likelihood

We propose a layered log-likelihood-ratio-based belief propagation(LLR-BP)algorithm for Low Density Parity Check (LDPC)codes. In the conventional decoding algorithm, the process of decoding would be terminated when it reaches the maximum iterative number or the near-convergence is achieved. The proposed algorithm is based on the variable node information quantification and stop updating criterion thought. By dividing the absolute value of the variable node to different layers, a part of the check nodes stop the iteration before reaching the maximum iterative number to save iterative time. From the simulation results, we know that the improved decoding algorithm successively achieves lower computation complexity than the conventional one .And the layered LLR-BP algorithm is a better scheme for LDPC codes.

scholarly journals A weighted group shuffled decoding for low-density parity-check codes

2022 ◽  
Vol 25 (1) ◽  
pp. 375
Author(s):  
Fatima Zahrae Zenkouar ◽  
Mustapha El Alaoui ◽  
Said Najah
Keyword(s):  
Belief Propagation ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Exponential Form ◽  
Exponential Factor ◽  
Short Cycle ◽  
Low Density Parity Check ◽  
Suggested Technique ◽  
Parity Check Codes

In this paper, we have developed several concepts such as the tree concept, the short cycle concept and the group shuffling concept of a propagation cycle to decrypt low-density parity-check (LDPC) codes. Thus, we proposed an algorithm based on group shuffling propagation where the probability of occurrence takes exponential form exponential factor appearance probability belief propagation-group shuffled belief propagation (EFAP-GSBP). This algorithm is used for wireless communication applications by providing improved decryption performance with low latency. To demonstrate the effectiveness of our suggested technique EFAP-GSBP, we ran numerous simulations that demonstrated that our algorithm is superior to the traditional BP/GSBP algorithm for decrypting LPDC codes in both regular and non-regular forms

scholarly journals Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1106
Author(s):  
Vladimir L. Petrović ◽  
Dragomir M. El Mezeni ◽  
Andreja Radošević
Keyword(s):  
Channel Coding ◽  
Parallel Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Case Scenario ◽  
New Radio ◽  
Physical Channel ◽  
Computationally Intensive ◽  
Hardware Processing ◽  
Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

scholarly journals Perturbed Adaptive Belief Propagation Decoding for High-Density Parity-Check Codes

2020 ◽  
pp. 1-1
Author(s):  
Li Deng ◽  
Zilong Liu ◽  
Yong Liang Guan ◽  
Xiaobei Liu ◽  
Chaudhry Adnan Aslam ◽  
...  
Keyword(s):  
Belief Propagation ◽  
High Density ◽  
Parity Check ◽  
Parity Check Codes
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