scholarly journals Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling

2021 ◽  
Vol 2021 (1) ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Belief Propagation ◽  
Parallel Architecture ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Parity Check ◽  
Codeword Length ◽  
Check Matrix ◽  
Field Programmable ◽  
On Chip ◽  
The Right

AbstractLayered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of $$E_b/N_0$$ E b / N 0 until the BER of 1e−6.

scholarly journals A Modified Shuffling Method to Reduce Decoding Complexity of QC-LDPC Codes

2020 ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Belief Propagation ◽  
Iterative Algorithms ◽  
Ldpc Codes ◽  
Parallel Architectures ◽  
Parity Check ◽  
Low Snr ◽  
Memory Overhead ◽  
Field Programmable ◽  
On Chip ◽  
The Right

Abstract Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.

scholarly journals Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 425
Author(s):  
Zhe Zhang ◽  
Liang Zhou ◽  
Zhi Heng Zhou
Keyword(s):  
Belief Propagation ◽  
Ldpc Code ◽  
Bp Algorithm ◽  
Parity Check ◽  
Parity Check Matrix ◽  
M Sequence ◽  
Check Matrix ◽  
Parallel Decoding ◽  
Maximum A Posterior ◽  
The Impact

An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10−5.

A Construction of Non Binary LDPC Codes by Circular Matrices

2014 ◽  
Vol 909 ◽  
pp. 338-341 ◽  
Author(s):  
Sekson Timakul ◽  
Somsak Choomchuay
Keyword(s):  
Bit Error Rate ◽  
Preliminary Investigation ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Code Rate ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Code Performance ◽  
Check Matrix ◽  
Better Than

In LDPC code, the structure of code's parity check matrix plays the crucial role in code performance. In this paper proposes the preliminary investigation of a designed parity check matrix from Tanner. We modify this technique in to non binary LDPC structure and decoding with FFT-SPA. We take into high code rate application more than 0.8. The result has shown that in bit error rate (BER) compare between non-binary LDPC and binary LDPC. In our results, the performance of non binary LDPC has better than binary LDPC.

Image Transmission Based on QC-LDPC Codes with Simple Recursive Encoding Form

2014 ◽  
Vol 602-605 ◽  
pp. 3223-3227
Author(s):  
Hua Xu
Keyword(s):  
Information Transfer ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Image Transmission ◽  
Parity Check ◽  
Extrinsic Information ◽  
Transmission Scheme ◽  
Check Matrix ◽  
Exponent Matrix ◽  
Base Matrix

Low encoding delay and complexity is very important for image transmission. This paper proposes a novel image transmission scheme with low encoding complexity. The proposed scheme is based on quasi-cyclic low density parity check (QC-LDPC) codes with a simple recursive encoding form (SREF QC-LDPC code) which results in low encoding complexity and delay. Constructing the SREF QC-LDPC codes in this scheme composes of two main steps, construction of the base matrix and the exponent matrix. We combine the differential evolution and protograph extrinsic information transfer (PEXIT) method to optimize the base matrix of QC-LDPC code. Consequently, the exponent matrix and the parity check matrix are constructed. Simulation results show that the proposed scheme based on SREF QC-LDPC code can provide a good tradeoff between the performance and complexity.

scholarly journals Investigation of random-structure regular LDPC codes construction based on progressive edge-growth and algorithms for removal of short cycles

2021 ◽  
Vol 4 (9(112)) ◽  
pp. 46-53
Author(s):  
Viktor Durcek ◽  
Michal Kuba ◽  
Milan Dado
Keyword(s):  
Hamming Distance ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Error Correcting Codes ◽  
Random Structure ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Tanner Graph ◽  
Check Matrix ◽  
Computer Based

This paper investigates the construction of random-structure LDPC (low-density parity-check) codes using Progressive Edge-Growth (PEG) algorithm and two proposed algorithms for removing short cycles (CB1 and CB2 algorithm; CB stands for Cycle Break). Progressive Edge-Growth is an algorithm for computer-based design of random-structure LDPC codes, the role of which is to generate a Tanner graph (a bipartite graph, which represents a parity-check matrix of an error-correcting channel code) with as few short cycles as possible. Short cycles, especially the shortest ones with a length of 4 edges, in Tanner graphs of LDPC codes can degrade the performance of their decoding algorithm, because after certain number of decoding iterations, the information sent through its edges is no longer independent. The main contribution of this paper is the unique approach to the process of removing short cycles in the form of CB2 algorithm, which erases edges from the code's parity-check matrix without decreasing the minimum Hamming distance of the code. The two cycle-removing algorithms can be used to improve the error-correcting performance of PEG-generated (or any other) LDPC codes and achieved results are provided. All these algorithms were used to create a PEG LDPC code which rivals the best-known PEG-generated LDPC code with similar parameters provided by one of the founders of LDPC codes. The methods for generating the mentioned error-correcting codes are described along with simulations which compare the error-correcting performance of the original codes generated by the PEG algorithm, the PEG codes processed by either CB1 or CB2 algorithm and also external PEG code published by one of the founders of LDPC codes

scholarly journals Influence of BCH and LDPC Code Parameters on the BER Characteristic of Satellite DVB Channels

2014 ◽  
Vol 4 (1) ◽  
pp. 591-595 ◽  
Author(s):  
L. Jordanova ◽  
L. Laskov ◽  
D. Dobrev
Keyword(s):  
Communication Channel ◽  
Noise Immunity ◽  
Radio Channel ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Channel Noise ◽  
Bch Code ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Check Matrix

This article presents the results of a study on the noise immunity of DVB channels when higher-order M-ary APSK modulation schemes and concatenated BCH-LDPC codes are used. Dependencies to determine the probability at the decoder output are given taking into consideration the BCH and LDPC code parameters and the error probability in the communication channel. The influence of the BCH packets length, the BCH code rate, the number of maximum iteration and the parameters of LDPC parity-check matrix on the code efficiency is analyzed. Research of the influence of the concatenated LDPC-BCH code parameters on the radio channel noise immunity is conducted and dependencies to determine the required CNR at the input of the satellite receiver are given.

scholarly journals Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1106
Author(s):  
Vladimir L. Petrović ◽  
Dragomir M. El Mezeni ◽  
Andreja Radošević
Keyword(s):  
Channel Coding ◽  
Parallel Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Case Scenario ◽  
New Radio ◽  
Physical Channel ◽  
Computationally Intensive ◽  
Hardware Processing ◽  
Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

New Optical Codes Based on Construction of Parity Check Matrix of LDPC Codes

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Mohammed Amine Tehami ◽  
Chahinaz Kandouci ◽  
Ali Djebbari
Keyword(s):  
Code Division Multiple Access ◽  
Cross Correlation ◽  
Direct Detection ◽  
Ldpc Codes ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Check Matrix ◽  
Eye Pattern ◽  
Balanced Detection ◽  
Code Division Multiple

AbstractIn this paper, new spectral optical codes based on the construction parity check matrix of LDPC codes were designed and implemented in an optical code-division multiple access communication system. Two types optical family codes can be obtained with respectively a cross correlation of {\lambda _c} = 0 and {\lambda _c} = 1. In each case, the codes can either be decoded using the direct detection or the balanced detection. Performance was evaluated by referring to the Q factor, the bit error rate and the eye pattern diagrams using Optisystem 9.0.

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