FPGA Implementation of Vedic Squarer for Communication Systems

2019 ◽  
Vol 09 ◽  
Author(s):  
Angshuman Khan ◽  
Sudip Halder ◽  
Souvik Saha ◽  
Rajeev Arya
Keyword(s):  
Impulse Response ◽  
Communication Systems ◽  
Finite Impulse Response ◽  
Fpga Implementation ◽  
Peak Amplitude ◽  
Fir Filters ◽  
Mathematical Function ◽  
Analog Multipliers ◽  
Frequency Doublers ◽  
Digital Multipliers

The squarer or squaring circuit is extensively used in communication systems as a mathematical function with applications of frequency doublers, finite impulse response (FIR) filters, peak amplitude detectors, digital processors and analog multipliers, etc. and especially for square law detection circuits. Vedic multipliers are popular mainly for it’s simplicity in the literature of digital multipliers. Recently proposed 2-bit square calculator or self-multiplier already took the attraction of the researchers. In this paper, two bits squarer or self-multiplier or square calculator has been successfully coded using VHDL, verified in Xilinx tool and finally implemented in popular FPGA Spartan kit.

Comparison of Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) Filters in Cardiac Optical Mapping Records

2021 ◽  
pp. 207-224
Author(s):  
David Rivas-Lalaleo ◽  
Sergio Muñoz-Romero ◽  
Monica Huerta ◽  
Víctor Bautista-Naranjo ◽  
Jorge García-Quintanilla ◽  
...  
Keyword(s):  
Impulse Response ◽  
Optical Mapping ◽  
Finite Impulse Response ◽  
Infinite Impulse Response ◽  
Fir Filters

NOVEL DESIGN AND FPGA IMPLEMENTATION OF DA-RNS FIR FILTERS

2004 ◽  
Vol 13 (06) ◽  
pp. 1233-1249 ◽  
Author(s):  
WEI WANG ◽  
M. N. S. SWAMY ◽  
M. O. AHMAD
Keyword(s):  
Power Efficiency ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Chinese Remainder Theorem ◽  
Low Cost ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Fpga Implementation ◽  
Fir Filters

Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).

Multiplierless Multiple-Stage Cascaded FIR Filter Design

2014 ◽  
Vol 24 (01) ◽  
pp. 1550011
Author(s):  
Wenbin Ye
Keyword(s):  
Impulse Response ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Single Stage ◽  
Fir Filters ◽  
Hardware Cost ◽  
Stage Design ◽  
Design Time ◽  
Fir Filter Design ◽  
Novel Algorithm

It is well known that multiplierless finite impulse response (FIR) filters in multiple-stage cascade form can achieve lower hardware cost and lower coefficient sensitivity than that of single stage design. In this work, a novel algorithm is proposed for the design of multiplierless multiple-stage cascaded FIR filters. Unlike to the conventional algorithms in which the number of stages is fixed and usually is fixed to two, the number of stage in the proposed algorithm is automatically determined. The design examples show that the proposed algorithm significantly outperforms the best existing algorithm in terms of hardware cost and the design time is also saved.

scholarly journals ONE SIMPLE METHOD FOR THE DESIGN OF MULTIPLIERLESS FIR FILTERS

2005 ◽  
Vol 3 (02) ◽  
Author(s):  
G. Jovanovic-Dolecek ◽  
M. M-Alvarez ◽  
M. Martinez
Keyword(s):  
Impulse Response ◽  
Finite Impulse Response ◽  
Second Order ◽  
Fir Filters ◽  
Simple Method ◽  
Prototype Filter ◽  
Repeated Use

This paper presents one simple method for the design of multiplierless finite Impulse response (FIR) filters by the repeated use of the same filter. The prototype filter Is a cascade of a second order recurslve running sum (RRS) filter, known as a cosine filter, and its corresponding expanded versions. As a result, no multipliers are requlred to implement this filter.

Efficient FIR Filter Architecture using FPGA

2020 ◽  
Vol 13 (1) ◽  
pp. 91-98
Author(s):  
Ahmed K. Jameil ◽  
Yassir A. Ahmed ◽  
Saad Albawi
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Fir Filters ◽  
Filter Architecture ◽  
Circuit Techniques ◽  
And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

Novel Methods to Design Low-Complexity Digital Finite Impulse Response (FIR) Filters

2018 ◽  
pp. 6234-6244
Author(s):  
David Ernesto Troncoso Romero ◽  
Gordana Jovanovic Dolecek
Keyword(s):  
Impulse Response ◽  
Digital Filters ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Low Complexity ◽  
Fir Filters ◽  
Linear Phase ◽  
Guaranteed Stability ◽  
Important Challenge ◽  
Dsp Systems

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

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