Network-on-Chip Especially for Video Coding Applications Using Multilayer Mesh Topology

2019 ◽  
Vol 12 (3) ◽  
pp. 247-256
Author(s):  
Kamel Messaoudi ◽  
Salah Toumi ◽  
El-Bay Bourennane
Keyword(s):  
Video Coding ◽  
Communication System ◽  
Data Transfer ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Topology ◽  
Global Interconnects ◽  
And Performance ◽  
On Chip ◽  
Scalable Communication

Background: Network on chip is proposed as new reusable and scalable communication system for applications with important number of IPs. The NoC architecture characteristics are based on several factors: the implementation strategy of IPs, the power dissipation, the placement of IPs, data transfer time, the requirements of the given application, etc. The N×M Mesh topology combined with the XY routing algorithm are generally chosen in many studies. Hardware IPs proposed in the literature, for various applications as example video encoders, operates at different frequencies and generally implemented according to several strategies and different bus sizes. Connecting these IPs using the same communication system is very difficult. Methods: In this paper, we present a new topology based on multi-layer mesh topology and adapted for video coding applications. The proposed topology exploits the video coding information regarding groups of cores that communicate through two cores only. The idea is to use a specific NoC for each group of cores and connect the NoCs with bridge in the positions of two communication cores. The choice of parameters in each NoC depends on the characteristic of IPs in the same group in order to maximize communication adaptivity and performance. Results: Synthesis results show that the proposed multi-layer mesh topology NoC uses much less resources than the traditional NxM mesh topology NoC. Conclusion: This reduction in term of resources is assured by the considerable reduction in the length and number of global interconnects, resulting in an increase in the performance and decrease in the power consumption and area of wire limited circuits.

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs

2019 ◽  
Vol 28 (12) ◽  
pp. 1950202 ◽  
Author(s):  
Khyamling Parane ◽  
B. M. Prabhu Prasad ◽  
Basavaraj Talawar
Keyword(s):  
Design Space Exploration ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Tree Topology ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
On Chip ◽  
Congestion Aware

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the [Formula: see text] mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the [Formula: see text] mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.

scholarly journals Parallel overloaded CDMA crossbar for network on chip

2019 ◽  
Vol 32 (1) ◽  
pp. 105-118
Author(s):  
Ashok Kumar ◽  
P. Dananjayan
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Large Network ◽  
Network Systems ◽  
Mesh Topology ◽  
Field Programmable ◽  
On Chip ◽  
Code Division Multiple

For high performance of Network on Chip (NoC), Code Division Multiple Access (CDMA) technique is used recently due to its fixed communication delay, reduced area utilisation and low power consumption. The CDMA system uses Walsh based spreading code which improves the bandwidth efficiency. On the contrary, it is not effective when the number of nodes present in the system increases. Overloaded CDMA (OCDMA) is presented for such large network systems. In this paper, OCDMA crossbar is modified and advanced with parallel encoding and decoding operation using orthogonal gold codes for improving the speed of crossbar thereby obtaining high performance in NoC switch. A modified crossbar consisting of extra processing elements is used to enhance the performance of NoC based System on Chip (SoC) system. This work is simulated on Xilinx tool and implemented in Vertex-6 (XC6VLX760) Field Programmable Gate Array (FPGA) device. The proposed work is implemented for four ports, eight ports and sixteen ports with deterministic X-Y routing algorithm in 3 3 NoC design with mesh topology. This NoC switch shows 9.79% improvement in delay and shows 20.76% improvement in power consumption when compared to the existing CDMA NoCs for 8 bit data packet.

scholarly journals Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

2018 ◽  
Vol 10 (2) ◽  
pp. 514
Author(s):  
Ng Yen Phing ◽  
M.N. Mohd Warip ◽  
Phaklen Ehkan ◽  
S.Y. Teo
Keyword(s):  
Power Consumption ◽  
Large Scale ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Total Power ◽  
Clustering Method ◽  
Mesh Topology ◽  
Total Power Consumption ◽  
Promising Solution ◽  
On Chip

<span lang="EN-US">Network-on-Chip (NoC) is a promising solution to overcome the communication problem of System-on-Chip (SoC) architecture. The execution of topology, routing algorithm and switching technique is significant because it powerfully affects the overall performance of NoC. In the Network-on-Chip, the total power consumption increasing due to the large scale of network. In order to solve it, a clustering method and disable cores and routers based on clustering method is apply onto mesh based NoC architecture. In the proposed approach, the optimization of total area and total power consumption are the major concern. Experiment results show that the proposed method outperformas the existing work. The clustering-mesh based method reduced the total area by 22% to 40 % and total power consumption by 22% to 56% compare to mesh topology. In addition, the proposed method by disable cores and routers based on clustering-mesh based method has decrease the total area by 45% to 87% and total power consumption by 33% to 75% compare to mesh topology.</span>

scholarly journals Load-balanced routing algorithm for Network-on-Chip employing fair arbiter

2021 ◽  
Vol 1871 (1) ◽  
pp. 012117
Author(s):  
Lu Liu ◽  
Yanfei Yang ◽  
Qianqian Lei ◽  
Huhu Wang ◽  
Song Lixun
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
On Chip ◽  
Load Balanced

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

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