The Coordinated Fault Current Limiting Strategy for a Hybrid Multilevel Modular Converter (MMC) based VSC-HVDC Applications

2021 ◽  
Vol 14 ◽  
Author(s):  
Muhammad Ahmad ◽  
Chunyang Gong ◽  
Yixin Chen ◽  
Zhixin Wang ◽  
Hui Li
Keyword(s):  
Power Transmission ◽  
Short Circuit ◽  
Circuit Breaker ◽  
High Capacity ◽  
Fault Current ◽  
Overhead Lines ◽  
Hvdc Transmission ◽  
High Voltage Direct Current ◽  
Current Limiting ◽  
Modular Converter

Background: High-voltage direct current (HVDC) is suitable for high capacity and longdistance power transmission, thus becoming ideal for connecting renewable energies such as solar power and wind power to grids. Objective: Overhead lines in HVDC are vulnerable to short-circuit faults. Non-permanent DC short circuit faults are the most common in HVDC transmission, which can lead to pause in power transmission and interruption in large grids. Thereby, it is crucial to deploy techniques to suppress fault current. Method: To lower the fault current economically, a coordinated fault current limiting strategy based on a hybrid multilevel modular converter (MMC) is proposed in this paper. Results: Combining hybrid MMC and small-capacity DC circuit breaker reduces total IGBTs required and avoids MMC blocking during pole-to-ground short-circuit fault. This approach is verified using a two-terminal MMC-based system in PSCAD/EMTDC simulation environment. Conclusion: By implementing the introduced scheme, the peak fault current can be lowered by 33.0% using hybrid-MMC with 80% of FBSMs. Economic efficiency can be improved by adopting proposed scheme.

scholarly journals Solid-State DC Circuit Breakers and their Comparison in Modular Multilevel Converter Based-HVDC Transmission System

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1204
Author(s):  
Gul Ahmad Ludin ◽  
Mohammad Amin Amin ◽  
Hidehito Matayoshi ◽  
Shriram S. Rangarajan ◽  
Ashraf M. Hemeida ◽  
...  
Keyword(s):  
Solid State ◽  
High Voltage ◽  
Direct Current ◽  
Circuit Breaker ◽  
Transmission System ◽  
Simulation Software ◽  
Fault Current ◽  
Circuit Breakers ◽  
Hvdc Transmission ◽  
Dc Circuit Breakers

This paper proposes a new and surge-less solid-state direct current (DC) circuit breaker in a high-voltage direct current (HVDC) transmission system to clear the short-circuit fault. The main purpose is the fast interruption and surge-voltage and over-current suppression capability analysis of the breaker during the fault. The breaker is equipped with series insulated-gate bipolar transistor (IGBT) switches to mitigate the stress of high voltage on the switches. Instead of conventional metal oxide varistor (MOV), the resistance–capacitance freewheeling diodes branch is used to bypass the high fault current and repress the over-voltage across the circuit breaker. The topology and different operation modes of the proposed breaker are discussed. In addition, to verify the effectiveness of the proposed circuit breaker, it is compared with two other types of surge-less solid-state DC circuit breakers in terms of surge-voltage and over-current suppression. For this purpose, MATLAB Simulink simulation software is used. The system is designed for the transmission of 20 MW power over a 120 km distance where the voltage of the transmission line is 220 kV. The results show that the fault current is interrupted in a very short time and the surge-voltage and over-current across the proposed breaker are considerably reduced compared to other topologies.

Design and Simulation of Breaking Time Sequence for DC Circuit Breaker with a Current-Limiting Inductance

2014 ◽  
Vol 556-562 ◽  
pp. 1959-1963
Author(s):  
Si Ming Wei ◽  
Yi Gong Zhang ◽  
Huan Liu ◽  
Zhi Qiang Dai ◽  
Xiao Du
Keyword(s):  
Design Method ◽  
Circuit Breaker ◽  
Time Sequence ◽  
Fault Current ◽  
Distribution Grid ◽  
Current Limiting ◽  
Selection Principles ◽  
Dc Circuit Breaker ◽  
Breaking Time ◽  
A Current

It is great significance for development of MTDC (Multi-terminal HVDC) to build DC transmission and distribution grids. However, the relatively low impedance in DC grids makes the fault penetration much faster and deeper .Consequently, fast and reliable DC circuit breaker is needed to isolate faults. Breaking time and other parameters are important for a breaker to achieve its goals. This paper presents a DC circuit breaker with a current-limiting inductance and gets the rising and falling characteristics of fault current. Based on the characteristics, a design method of breaking time sequence will be given, as well as the calculation of current-limiting inductance and the selection principles of arresters. A 10kV DC distribution grid is modeled and simulated by PSCAD/EMTDC to verify that the method can meet the requirements of breaking fault current quickly and reliably.

scholarly journals A Novel Overcurrent Suppression Strategy during Reclosing Process of MMC-HVDC

2019 ◽  
Vol 9 (9) ◽  
pp. 1737 ◽  
Author(s):  
Bin Jiang ◽  
Yanfeng Gong
Keyword(s):  
Transmission Lines ◽  
Short Circuit ◽  
Current Method ◽  
Short Circuit Current ◽  
Simulation Software ◽  
Fault Current ◽  
Overhead Lines ◽  
Hvdc System ◽  
Electromagnetic Transient Simulation ◽  
Current Calculation

A modular multilevel converter based high-voltage DC (MMC-HVDC) system has been the most promising topology for HVDC. A reclosing scheme is usually configured because temporary faults often occur on transmission lines especially when overhead lines are used, which often brings about an overcurrent problem. In this paper, a new fault current limiter (FCL) based on reclosing current limiting resistance (RCLR) is proposed to solve the overcurrent problem during the reclosing process. Firstly, a mesh current method (MCM) based short-circuit current calculation method is newly proposed to solve the fault current calculation of a loop MMC-HVDC grid. Then the method to calculate the RCLR is proposed based on the arm current to limit the arm currents to a specified value during the reclosing process. Finally, a three-terminal loop MMC-HVDC test grid is constructed in the widely used electromagnetic transient simulation software PSCAD/EMTDC and the simulations prove the effectiveness of the proposed strategy.

scholarly journals Minimum Short Circuit Ratio Requirement for MMC-HVDC Systems Based on Small-Signal Stability Analysis

Energies ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 3283 ◽  
Author(s):  
Zheren Zhang ◽  
Liang Xiao ◽  
Guoteng Wang ◽  
Jian Yang ◽  
Zheng Xu
Keyword(s):  
Reactive Power ◽  
Short Circuit ◽  
Small Signal ◽  
Small Signal Stability ◽  
Ratio Requirement ◽  
Planning Stage ◽  
Hvdc System ◽  
Hvdc Transmission ◽  
High Voltage Direct Current ◽  
Signal Stability

This paper determines the minimum short circuit ratio (SCR) requirement for a modular multilevel converter based high-voltage direct current (MMC-HVDC) transmission systems. Firstly, a simplified model of MMC is introduced; the MMC is represented by its AC and DC side equivalent circuit. Next, by linearizing the MMC subsystem and the DC network subsystem, the deduction of the small-signal models of MMC subsystem, the small-signal model of the DC network and MMC-HVDC are carried out successively. Thirdly, the procedure for determining the minimum SCR requirement of MMC-HVDC is described. Finally, case studies are performed on a two-terminal MMC-HVDC system under four typical control schemes. The results show that the restraint factors for the rectifier MMC is predominantly the voltage safety limit constraint, and the restraint factors for the inverter MMC are mainly the phase locked loop (PLL) or the outer reactive power controller. It is suggested that the minimum SCR requirement for the sending and the receiving systems should be 2.0 and 1.5 in the planning stage.

scholarly journals A Selective Fault Clearing Scheme for a Hybrid VSC-LCC Multi-Terminal HVdc System

Energies ◽  
2020 ◽  
Vol 13 (14) ◽  
pp. 3554
Author(s):  
Naushath M. Haleem ◽  
Athula D. Rajapakse ◽  
Aniruddha M. Gole ◽  
Ioni T. Fernando
Keyword(s):  
High Capacity ◽  
Voltage Source ◽  
Voltage Source Converter ◽  
Circuit Breakers ◽  
Hvdc System ◽  
Hvdc Transmission ◽  
High Voltage Direct Current ◽  
Clearing Functions ◽  
Transmission Structure ◽  
The Impact

A selective fault clearing scheme is proposed for a hybrid voltage source converter (VSC)-line commutated converter (LCC) multi-terminal high voltage direct current (HVdc) transmission structure in which two small capacity VSC stations tap into the main transmission line of a high capacity LCC-HVdc link. The use of dc circuit breakers (dc CBs) on the branches connecting to VSCs at the tapping points is explored to minimize the impact of tapping on the reliability of the main LCC link. This arrangement allows clearing of temporary faults on the main LCC line as usual by force retardation of the LCC rectifier. The faults on the branches connecting to VSC stations can be cleared by blocking insulated gate bipolar transistors (IGBTs) and opening ac circuit breakers (ac CB), without affecting the main line’s performance. A local voltage and current measurement based fault discrimination scheme is developed to identify the faulted sections and pole(s), and trigger appropriate fault recovery functions. This fault discrimination scheme is capable of detecting and discriminating short circuits and high resistances faults in any branch well before 2 ms. For the test grid considered, 6 kA, 2 ms dc CBs can easily facilitate the intended fault clearing functions and maintain the power transfer through healthy pole during single-pole faults.

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