Block cipher four implementation on field programmable gate array

Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.

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Design and Implementation of a RISC Processor on FPGA

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.981.58 ◽

2014 ◽

Vol 981 ◽

pp. 58-61 ◽

Cited By ~ 1

Author(s):

Hui Jing Yang ◽

Hao Fan ◽

Huai Guo Dong

Keyword(s):

Experimental Data ◽

Computer Architecture ◽

Field Programmable Gate Array ◽

General Purpose ◽

Input Output ◽

Verilog Hdl ◽

Design And Implementation ◽

Risc Processor ◽

Field Programmable ◽

Clock Oscillator

This paper targets the computer architecture courses and presents an Field Programmable Gate Array implementation of a RISC Processor via Verilog HDL design. It has 8-bit instruction words and 4 general purpose registers. It have two instruction formats. And it has been designed with Verilog HDL, synthesized using Quatus II 12.0, simulated using ModelSim simulator, and then implemented on Altera Cyclone IV FPGA that has 484 available Input/Output pins and 50MHz clock oscillator. The final overall simulation's experimental data verify the correctness of the processor.

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Design and implementation of proposed 320 bit RC6-cascaded encryption/decryption cores on altera FPGA

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v10i6.pp6370-6379 ◽

2020 ◽

Vol 10 (6) ◽

pp. 6370

Author(s):

Ashwaq T. Hashim ◽

Ahmed M. Hasan ◽

Hayder M. Abbas

Keyword(s):

Field Programmable Gate Array ◽

Block Cipher ◽

Low Cost ◽

Structure Design ◽

Secret Key ◽

Design And Implementation ◽

Cryptographic Algorithm ◽

Field Programmable ◽

Key Block ◽

Encryption Decryption

This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.

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The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.571.534 ◽

2012 ◽

Vol 571 ◽

pp. 534-537

Author(s):

Bao Feng Zhang ◽

De Hu Man ◽

Jun Chao Zhu

Keyword(s):

Signal Processing ◽

Real Time ◽

Field Programmable Gate Array ◽

Distributed Algorithm ◽

Design Method ◽

Fir Filter ◽

Experimental Results ◽

Linear Phase ◽

Design And Implementation ◽

Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

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