Block cipher four implementation on field programmable gate array

Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.

Extending PowerPack for Profiling and Analysis of High-Performance Accelerator-Based Systems

Accelerators offer a substantial increase in efficiency for high-performance systems offering speedups for computational applications that leverage hardware support for highly-parallel codes. However, the power use of some accelerators exceeds 200 watts at idle which means use at exascale comes at a significant increase in power at a time when we face a power ceiling of about 20 megawatts. Despite the growing domination of accelerator-based systems in the Top500 and Green500 lists of fastest and most efficient supercomputers, there are few detailed studies comparing the power and energy use of common accelerators. In this work, we conduct detailed experimental studies of the power usage and distribution of Xeon-Phi-based systems in comparison to the NVIDIA Tesla and an Intel Sandy Bridge multicore host processor. In contrast to previous work, we focus on separating individual component power and correlating power use to code behavior. Our results help explain the causes of power-performance scalability for a set of HPC applications.

Design of SCR Control Software Based on Dual-Core Processor

This paper introduces the control software of SCR system based on the dual-core processor S12XEP100. By the reasonable coordination between the host processor and the coprocessor XGATE, the SCR control system satisfies the increasing demands for real-time. Control performance tests show that the control software of SCR system meets the basic control requirements, also improves the real-time performance of programs effectively, such as urea injection frequency, urea injection quantity and the stability of common rail pipe pressure.

Design and Development of Stream Processor Architecture for GPU Application Using Reconfigurable Computing

Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. Stream processor consists of clusters of functional units which provide a bandwidth hierarchy, supporting hundreds of arithmetic units. The arithmetic cluster units are designed to exploit instruction level parallelism and subword parallelism within a cluster and data parallelism across the clusters.For decreasing the area and power, a single controller is used to control data flow between clusters and between host processor and GPU. The designed of stream processor unit has been carried out in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.The simulated execution time of 8-bit pipelined multiplier is 60 ps and 100 ns for 8-bit pipelined adder while operating at 90 MHz.

Research of Intelligent Control System for Fish-Farming

Used Atmega 8 microcontroller as the control center, with the temperature sensor DS18B20, feeding control system, combined with radio frequency technology, intelligent control system for fish-farming was designed. The system has the whole process of intelligent automatic control and testing for feeding, supplemental oxygen, and PID temperature regulation; PC and the host processor connect each other through the RS-485 to greatly improve the transmission distance, using CRC cyclic redundancy check code ensure the accuracy of data. The machine is mainly responsible for collecting the spot parameters such as temperature and transmitting the data to the host processor, and send data to PC by the host processor through the serial port to display. Using GSM short message service directly sends the relevant data to the console or the owner of the mobile phone, so as to realize the entire fish process automation management. The system can be widely used in families, and pond pisciculture, and provides the owners efficient and convenient services.

Design of the Wireless Power Acquisition Node Based on the LONWORKS and ZIGBEE Technology

ZIGBEE and LONWORKS related technologies are the current research focus in the area of the communication, and it plays a great part in the development of the intelligent building. At the same time, how to collect the power parameter accurately is in urgent need in the intelligent building. We take the CC2430 of the TI Corporation as the host processor, the Neuron 3150 of the Echelon Corporation as the coprocessor to build the communication system, and use the ATT7022 chip to collect power parameters, so we can control and monitor the power through this communication system.

On The Design of Secure ATM System

Over the past three decades, consumers have been largely depending on and trust the Automatic Teller Machine, better known as ATM machine to conveniently meet their banking needs. ATM is a data terminal, it has to be connected to, and communicate through, a host processor. The host processor may be owned by a bank or any financial institution, or it may be owned by an independent service provider. Moreover, an ATM can support multiple ATM cards owned by different financial institutions or banks. Most host processors can support leased-line or dial-up machines. However, despite the numerous advantages of ATM system, ATM fraud has recently become more widespread. Recent occurrences of ATM fraud range from techniques such as shoulder surfing and card skimming to highly advanced techniques involving fraudulent mobile alerts, and account takeover via stolen information and call centers, software tampering and/or hardware modifications to divert, or trap the dispensed currency. In this chapter, we provide a comprehensive overview of the possible fraudulent activities that may be perpetrated against ATMs and investigates recommended approaches to prevent or deter these types of frauds. In particular we develop a model for the utilization of biometrics equipped ATM to provide security solution against must of the well-known breaches associated with the current ATM system practice.

Parallelization and Performance Evaluation of an Edge Detection Algorithm on a Streaming Multi-Core Engine

In the world of multi-core processors, the STI Cell Broadband Engine (BE) stands out as a heterogeneous 9-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to improve upon conventional processors in graphics and related areas by integrating 8 computation engines each with multiple execution units and large register sets to achieve a high performance per area return. In this paper, we discuss the parallelization, implementation and performance evaluation of an edge detection image processing application based on the Roberts edge detector on the Cell BE. The authors report the edge detection performance measured on a computer with one Cell processor and with varying numbers of synergic processor engines enabled. These results are compared to the results obtained on the Cell’s single PPE with all 8 SPEs disabled. The results indicate that edge detection performs 10 times faster on the Cell BE than on modern RISC processors.