Reconstruction of the phase dynamics of the somitogenesis clock oscillator

In this study we develop a computational framework for the reconstruction of the phase dynamics of the somitogenesis clock oscillator. Our understanding of the somitogenesis clock, a developmental oscillator found in the vertebrate embryo, has been revolutionised by the development of real time reporters of clock gene expression. However, the signals obtained from the real time reporters are typically noisy, nonstationary and spatiotemporally dynamic and there are open questions with regard to how post-processing can be used to both improve the insight gained from a given experiment and to constrain theoretical models. In this study we present a methodology, which is a variant of empirical mode decomposition, that reconstructs the phase dynamics of the somitogenesis clock. After validating the methodology using synthetic datasets, we define a set of metrics that use the reconstructed phase profiles to infer biologically meaningful quantities. We perform experiments in which the signal from a real time reporter of the somitogenesis clock is recorded and reconstruct the phase dynamics. Application of the defined metrics yields results that are consistent with previous experimental observations. Moreover, we extend previous work by developing a gradient descent method for defining automated kymographs and showing that boundary conditions are non-homogeneous. By studying phase dynamics along phase gradient descent trajectories, we show that, consistent with a previous theoretical model, the oscillation frequency is inversely correlated with the phase gradient but that the coefficient is not constant in time. The proposed methodology provides a tool kit for that can be used in the analysis of future experiments and the quantitative observations can be used to guide the development of future mathematical models.

Design and Implementation of a RISC Processor on FPGA

This paper targets the computer architecture courses and presents an Field Programmable Gate Array implementation of a RISC Processor via Verilog HDL design. It has 8-bit instruction words and 4 general purpose registers. It have two instruction formats. And it has been designed with Verilog HDL, synthesized using Quatus II 12.0, simulated using ModelSim simulator, and then implemented on Altera Cyclone IV FPGA that has 484 available Input/Output pins and 50MHz clock oscillator. The final overall simulation's experimental data verify the correctness of the processor.