scholarly journals Design and implementation of proposed 320 bit RC6-cascaded encryption/decryption cores on altera FPGA

2020 ◽  
Vol 10 (6) ◽  
pp. 6370
Author(s):  
Ashwaq T. Hashim ◽  
Ahmed M. Hasan ◽  
Hayder M. Abbas
Keyword(s):  
Field Programmable Gate Array ◽  
Block Cipher ◽  
Low Cost ◽  
Structure Design ◽  
Secret Key ◽  
Design And Implementation ◽  
Cryptographic Algorithm ◽  
Field Programmable ◽  
Key Block ◽  
Encryption Decryption

This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.

scholarly journals Block cipher four implementation on field programmable gate array

2020 ◽  
Vol 5 (2) ◽  
pp. 53-64
Author(s):  
Yusuf Kurniawan ◽  
Muhammad Adli Rizqulloh
Keyword(s):  
Information Systems ◽  
Embedded Systems ◽  
Efficient Method ◽  
Field Programmable Gate Array ◽  
Block Cipher ◽  
Input Output ◽  
Nios Ii ◽  
Design And Implementation ◽  
Field Programmable ◽  
Host Processor

Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

Cryptanalytic Attacks on IDEA Block Cipher

2016 ◽  
Vol 66 (6) ◽  
pp. 582 ◽  
Author(s):  
Harish Kumar Sahu ◽  
Vikas Jadhav ◽  
Shefali Sonavane ◽  
R.K. Sharma
Keyword(s):  
Block Cipher ◽  
Data Encryption ◽  
Secret Key ◽  
Data Confidentiality ◽  
Data Encryption Standard ◽  
Financial Application ◽  
Time Requirements ◽  
International Data ◽  
Key Block ◽  
Symmetric Key

International data encryption algorithm (IDEA) is a secret key or symmetric key block cipher. The purpose of IDEA was to replace data encryption standard (DES) cipher, which became practically insecure due to its small key size of 56 bits and increase in computational power of systems. IDEA cipher mainly to provide data confidentiality in variety of applications such as commercial and financial application e.g. pretty good privacy (PGP) protocol. Till 2015, no successful linear or algebraic weaknesses IDEA of have been reported. In this paper, author explained IDEA cipher, its application in PGP and did a systematic survey of various attacks attempted on IDEA cipher. The best cryptanalysis result which applied to all keys could break IDEA up to 6 rounds out of 8.5 rounds of the full IDEA cipher1. But the attack requires 264 known plaintexts and 2126.8 operations for reduced round version. This attack is practically not feasible due to above mention mammoth data and time requirements. So IDEA cipher is still completely secure for practical usage. PGP v2.0 uses IDEA cipher in place of BassOmatic which was found to be insecure for providing data confidentiality.

Design and Implementation of RAM Operation Conflict Arbiter IC in LED/LCD Display Control System

2012 ◽  
Vol 268-270 ◽  
pp. 1574-1577
Author(s):  
Zhao Jie ◽  
Fei Yu ◽  
Jing Xia Wang ◽  
Liu Li
Keyword(s):  
Control System ◽  
Low Cost ◽  
Structure Design ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
System A ◽  
Lcd Display ◽  
Working Principle ◽  
Fpga Chip ◽  
Display Control

To solve the writing and reading operation conflict to RAM in LED/LCD display control system, a new RAM operation conflict arbiter IC was proposed. Comparing the traditional dual ports RAM, the IC has the advantages of low-cost and high stability. By analyzing the working principle and structure design, the IC was designed in pure digital way with Verilog HDL, and passed the simulation verify. Finally the IC was realized by Alter FPGA chip and passed the actual test.

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