A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems

Jiongyao Ye; Hongfeng Ding; Yingtao Hu; Takahiro Watanabe

doi:10.2197/ipsjjip.20.26

A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems

Journal of Information Processing ◽

10.2197/ipsjjip.20.26 ◽

2012 ◽

Vol 20 (1) ◽

pp. 26-36 ◽

Cited By ~ 1

Author(s):

Jiongyao Ye ◽

Hongfeng Ding ◽

Yingtao Hu ◽

Takahiro Watanabe

Keyword(s):

Embedded Systems ◽

Low Power ◽

Power Set ◽

Access Mode ◽

Behavior Based

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A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/jertcs.2013040103 ◽

2013 ◽

Vol 4 (2) ◽

pp. 50-61

Author(s):

Yul Chu ◽

Marven Calagos

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Access Time ◽

Data Cache ◽

Instruction Cache ◽

Prediction Mode ◽

Access Mode ◽

Cache Scheme ◽

Better Than

This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP (energy delay product) up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.

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A Study of Airport Access Mode Choice Behavior Based on a Nest Logit Model

CICTP 2020 ◽

10.1061/9780784482933.368 ◽

2020 ◽

Author(s):

Yuyao Bai ◽

Shaozhi Hong ◽

Xintian Liu

Keyword(s):

Logit Model ◽

Choice Behavior ◽

Mode Choice ◽

Access Mode ◽

Behavior Based ◽

Airport Access

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Efficient Instruction and Data Caching for High Performance Embedded Processors

Jornada de Jóvenes Investigadores del I3A ◽

10.26754/jji-i3a.201201788 ◽

1970 ◽

pp. 9

Author(s):

A. Ferrerón Labari ◽

D. Suárez Gracia ◽

V. Viñals Yúfera

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Interconnection Networks ◽

High Performance ◽

Critical Issue ◽

Content Management ◽

Structure Design ◽

Portable Devices ◽

On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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