A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

2013 ◽  
Vol 4 (2) ◽  
pp. 50-61
Author(s):  
Yul Chu ◽  
Marven Calagos
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Access Time ◽  
Data Cache ◽  
Instruction Cache ◽  
Prediction Mode ◽  
Access Mode ◽  
Cache Scheme ◽  
Better Than

This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP (energy delay product) up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

2021 ◽  
Author(s):  
T. Santosh Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Reduction Technique ◽  
Leakage Currents ◽  
Leakage Reduction ◽  
Sram Cell ◽  
Supply Voltage Scaling ◽  
Better Than

Abstract The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

scholarly journals Power Saving MAC Protocols for Wireless Body Area Networks (WBANs)

2021 ◽  
Author(s):  
Kheesheshta Ramgoolam ◽  
Vandana Bassoo
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Mac Protocol ◽  
Body Area Networks ◽  
Wireless Body Area Networks ◽  
Mac Protocols ◽  
Body Area ◽  
Traffic Scenario ◽  
Low Traffic ◽  
Better Than

Abstract Two important criteria of Wireless Body Area Networks (WBANs) are low power consumption and delay. These criteria can be met by designing efficient Medium Access Control (MAC) protocols. In this paper, two TDMA-based MAC protocols are proposed. The first protocol, TM-MAC makes use of only a main radio. The second proposed protocol, TWM-MAC makes use of a WUR alongside the main radio. The two proposed protocols are compared with different categories of standard MAC protocols and it is shown that they outperform the standard ones by improving the power consumption and delay. The TWM-MAC consumes 55% less power consumption than the Scheduled Channel Polling MAC (SCP-MAC) protocol for a high traffic scenario on the high-rate platform while the TM-MAC consumes 85% less power consumption than the SCP-MAC. For a low traffic scenario, the TWM-MAC performs 53.5% better than the SCP-MAC protocol and 77.5% better than the Very Low Power MAC (VLPM) protocol on the high and low-rate platforms respectively. An improvement in delay was observed with the TWM-MAC protocol for high traffic situations. The TWM-MAC protocol surpasses the VLPM protocol by 81.1% in terms of latency for a high traffic scenario and 3.2% for a low traffic scenario.

scholarly journals Oil Spill Identification from SAR Images for Low Power Embedded Systems Using CNN

2021 ◽  
Vol 13 (18) ◽  
pp. 3606
Author(s):  
Lorenzo Diana ◽  
Jia Xu ◽  
Luca Fanucci
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Oil Spills ◽  
Weather Conditions ◽  
Hardware Accelerators ◽  
Sar Images ◽  
Satellite Systems ◽  
High Resolution Images ◽  
Dedicated Hardware

Oil spills represent one of the major threats to marine ecosystems. Satellite synthetic-aperture radar (SAR) sensors have been widely used to identify oil spills due to their ability to provide high resolution images during day and night under all weather conditions. In recent years, the use of artificial intelligence (AI) systems, especially convolutional neural networks (CNNs), have led to many important improvements in performing this task. However, most of the previous solutions to this problem have focused on obtaining the best performance under the assumption that there are no constraints on the amount of hardware resources being used. For this reason, the amounts of hardware resources such as memory and power consumption required by previous solutions make them unsuitable for remote embedded systems such as nano and micro-satellites, which usually have very limited hardware capability and very strict limits on power consumption. In this paper, we present a CNN architecture for semantically segmenting SAR images into multiple classes. The proposed CNN is specifically designed to run on remote embedded systems, which have very limited hardware capability and strict limits on power consumption. Even if the performance in terms of results accuracy does not represent a step forward compared with previous solutions, the presented CNN has the important advantage of being able to run on remote embedded systems with limited hardware resources while achieving good performance. The presented CNN is compatible with dedicated hardware accelerators available on the market due to its low memory footprint and small size. It also provides many additional very significant advantages, such as having shorter inference times, requiring shorter training times, and avoiding transmission of irrelevant data. Our goal is to allow embedded low power remote devices such as satellite systems for remote sensing to be able to directly run CNNs on board, so that the amount of data that needs to be transmitted to ground and processed on ground can be substantially reduced, which will be greatly beneficial in significantly reducing the amount of time needed for identification of oil spills from SAR images.

scholarly journals A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems

2012 ◽  
Vol 20 (1) ◽  
pp. 26-36 ◽  
Author(s):  
Jiongyao Ye ◽  
Hongfeng Ding ◽  
Yingtao Hu ◽  
Takahiro Watanabe
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
Power Set ◽  
Access Mode ◽  
Behavior Based

scholarly journals An Area Efficient Low Power Data Cache for Multimedia Embedded Systems

2006 ◽  
Vol 13A (2) ◽  
pp. 101-110
Author(s):  
Cheong-Ghil Kim ◽  
Shin-Dug Kim
Keyword(s):  
Embedded Systems ◽  
Low Power ◽  
Data Cache ◽  
Area Efficient

scholarly journals Low-Power On-Chip Implementation of Enhanced SVM Algorithm for Sensors Fusion-Based Activity Classification in Lightweighted Edge Devices

Electronics ◽  
2022 ◽  
Vol 11 (1) ◽  
pp. 139
Author(s):  
Juneseo Chang ◽  
Myeongjin Kang ◽  
Daejin Park
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Smart Home ◽  
Input Data ◽  
Data Preprocessing ◽  
Training Data ◽  
Memory Usage ◽  
Activity Classification ◽  
Activity Data

Smart homes assist users by providing convenient services from activity classification with the help of machine learning (ML) technology. However, most of the conventional high-performance ML algorithms require relatively high power consumption and memory usage due to their complex structure. Moreover, previous studies on lightweight ML/DL models for human activity classification still require relatively high resources for extremely resource-limited embedded systems; thus, they are inapplicable for smart homes’ embedded system environments. Therefore, in this study, we propose a low-power, memory-efficient, high-speed ML algorithm for smart home activity data classification suitable for an extremely resource-constrained environment. We propose a method for comprehending smart home activity data as image data, hence using the MNIST dataset as a substitute for real-world activity data. The proposed ML algorithm consists of three parts: data preprocessing, training, and classification. In data preprocessing, training data of the same label are grouped into further detailed clusters. The training process generates hyperplanes by accumulating and thresholding from each cluster of preprocessed data. Finally, the classification process classifies input data by calculating the similarity between the input data and each hyperplane using the bitwise-operation-based error function. We verified our algorithm on `Raspberry Pi 3’ and `STM32 Discovery board’ embedded systems by loading trained hyperplanes and performing classification on 1000 training data. Compared to a linear support vector machine implemented from Tensorflow Lite, the proposed algorithm improved memory usage to 15.41%, power consumption to 41.7%, performance up to 50.4%, and power per accuracy to 39.2%. Moreover, compared to a convolutional neural network model, the proposed model improved memory usage to 15.41%, power consumption to 61.17%, performance to 57.6%, and power per accuracy to 55.4%.

Instruction Format Design for Low Power Embedded Systems

2015 ◽  
Vol 789-790 ◽  
pp. 829-832
Author(s):  
Jong Hee M. Youn ◽  
Dae Jin Park ◽  
Jeong Hun Cho ◽  
Doo San Cho
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Digital Circuit ◽  
Total Power ◽  
Switching Activity ◽  
Design Constraint ◽  
Instruction Fetch ◽  
Total Power Consumption ◽  
Instruction Format

Embedded systems demand to take high performance while executing on batteries. In such environment, the systems must be optimized with available technique to reduce energy consumption while not sacrificing performance. Especially, in mobile devices, power consumption is an important design constraint. Switching activity accounts for over 90% of total power consumption in a digital circuit. In this paper, we describe an approach to design instruction format for low power instruction fetch. The proposed method reduces switching activity of the instruction fetch logic by using a heuristic that minimizes switching between adjacent instructions. To do this, the proposed approach encodes opcodes so that frequently executed instruction pairs have smaller bit changes.

Vulnerabilities of Secure and Reliable Low-Power Embedded Systems and Their Analysis Methods

2014 ◽  
pp. 102-122
Author(s):  
Norbert Druml ◽  
Manuel Menghin ◽  
Christian Steger ◽  
Armin Krieg ◽  
Andreas Genser ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Mobile Devices ◽  
Development Process ◽  
Supply Voltage ◽  
Personal Data ◽  
Low Power Design ◽  
Fault Attacks ◽  
Wide Range

Due to the increase in popularity of mobile devices, it has become necessary to develop a low-power design methodology in order to build complex embedded systems with the ability to minimize power usage. In order to fulfill power constraints and security constraints if personal data is involved, test and verification of a design's functionality are imperative tasks during a product's development process. Currently, in the field of secure and reliable low-power embedded systems, issues such as peak power consumption, supply voltage variations, and fault attacks are the most troublesome. This chapter presents a comprehensive study over design analysis methodologies that have been presented in recent years in literature. During a long-lasting and successful cooperation between industry and academia, several of these techniques have been evaluated, and the identified sensitivities of embedded systems are presented. This includes a wide range of problem groups, from power and supply-related issues to operational faults caused by attacks as well as reliability topics.

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