scholarly journals Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

2019 ◽  
Author(s):  
Jieru Zhao ◽  
Tingyuan Liang ◽  
Sharad Sinha ◽  
Wei Zhang
Keyword(s):  
Machine Learning ◽  
High Level Synthesis ◽  
Congestion Prediction ◽  
Routing Congestion ◽  
High Level

scholarly journals Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 205
Author(s):  
Hamoud Younes ◽  
Ali Ibrahim ◽  
Mostafa Rizk ◽  
Maurizio Valle
Keyword(s):  
Machine Learning ◽  
State Of The Art ◽  
Machine Learning Algorithms ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Approximate Computing ◽  
Classification Framework ◽  
Time Latency ◽  
High Level

Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Machine (SVM) classifier with algorithmic level ACTs using High-Level Synthesis (HLS). A touch modality classification framework was adopted to validate the effectiveness of the proposed implementation. When compared to exact implementation presented in the state-of-the-art, the proposed implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2×. Moreover, the hardware resources are reduced by 40% while consuming 82% less energy in classifying an input touch with an accuracy loss less than 5%.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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