scholarly journals A Holding Voltage Adjustment Technique of SCR for ESD Protection

2017 ◽  
Keyword(s):  
Esd Protection

Design of a Dual-directional Diode-triggered SCR for Low Voltage ESD Protection

2020 ◽  
Vol 140 (6) ◽  
pp. 673-674
Author(s):  
Qiang Xu ◽  
Hailian Liang ◽  
Xiaofeng Gu
Keyword(s):  
Low Voltage ◽  
Esd Protection

A transient macro model of GGNMOS used in white LED driver ESD protection simulation

2014 ◽  
Author(s):  
Yu-xi Jiang ◽  
Mao-ze Li ◽  
Jiao Li ◽  
Gao-chuang Bai ◽  
Yuan-zhang Guo ◽  
...  
Keyword(s):  
White Led ◽  
Led Driver ◽  
Macro Model ◽  
Esd Protection ◽  
White Led Driver

Internal-Distributed CDM ESD Protection

2021 ◽  
Author(s):  
Mengfu Di ◽  
Zijin Pan ◽  
Cheng Li ◽  
Albert Wang
Keyword(s):  
Esd Protection

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

scholarly journals SCR-Based ESD Protection Using a Penta-Well for 5 V Applications

2018 ◽  
Vol 6 ◽  
pp. 691-695 ◽  
Author(s):  
Bo-Bae Song ◽  
Kyoung-Il Do ◽  
Yong-Seo Koo
Keyword(s):  
Esd Protection
Sign in / Sign up

Export Citation Format

Share Document