scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

Damage analysis in smart-power technology electrostatic discharge (ESD) protection devices

1999 ◽  
Vol 39 (6-7) ◽  
pp. 1143-1148 ◽  
Author(s):  
D. Pogany ◽  
N. Seliger ◽  
M. Litzenberger ◽  
H. Gossner ◽  
M. Stecher ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Damage Analysis ◽  
Smart Power ◽  
Esd Protection ◽  
Protection Devices

ESD Robustness Designs for the HV Power DEMOS

2012 ◽  
Vol 271-272 ◽  
pp. 1286-1290
Author(s):  
Shen Li Chen ◽  
Chi Ling Chu
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Unit Area ◽  
The Other ◽  
Esd Protection ◽  
Protection Devices ◽  
Protection Circuits

Two kinds of efficient electrostatic discharge (ESD) protection circuits in lateral drain extended MOSFETs (DEMOSFETs) will be designed and investigated in this paper. One kind of these test samples is fabricated with an SCR structure, which has the lowest turned-on resistance when it is triggered by a high voltage of ESD event. The SCR circuit is the most efficient of all protection devices in terms of ESD performance per unit area. Furthermore, the other type of these DUTs is an SCR with RC-triggered structure, which will have a small trigger voltage (Vt1) under ESD event, and then it obtains a good ESD immunity level.

A Contactless Sensing Analysis of a CUP Wafer

2013 ◽  
Vol 706-708 ◽  
pp. 1720-1725
Author(s):  
Shen Li Chen ◽  
Yang Shiung Cheng
Keyword(s):  
Electrostatic Discharge ◽  
Pulse Waveform ◽  
Design Rules ◽  
Strong Signal ◽  
Esd Protection ◽  
Protection Devices ◽  
Protection Circuits ◽  
Cmos Processes

The detected structures in a CUP wafer by sensing (leakage) analysis are presented in this paper. The pad structures are designed by the ADS2009 & TSMC 0.18um CMOS processes design rules, and use some electrostatic discharge (ESD) protection devices and circuits under these pads. Furthermore, the signal will be passed through these ESD devices or circuits on the top-metal pad as a sinusoidal, square, or ESD pulse waveform being injected. It is found that during an ESD occurred situation, a strong signal coupling can be sensed by the ESD protection circuits.

Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level

2016 ◽  
Vol 26 (02) ◽  
pp. 1750023
Author(s):  
Minoh Son ◽  
Changkun Park
Keyword(s):  
Integrated Circuits ◽  
Cmos Technology ◽  
Thermal Source ◽  
Esd Protection ◽  
A Cell ◽  
Protection Devices ◽  
Layout Technique ◽  
Typical Layout ◽  
Zigzag Shape ◽  
Survival Level

In this study, we propose cell-based diodes which are laid out with a zigzag shape as electrostatic discharge (ESD) protection elements to enhance the ESD survival level of the diodes. Generally, diodes are regarded as simple ESD protection devices in integrated circuits. During ESD events, the P–N junction of the ESD diode acts as a thermal source. In this study, we investigate a distributed layout method which relies on a cell-based ESD diode to prevent an excessive increase in the temperature at the P–N junction. However, although the distributed layout enhances the ESD survival levels of the ESD diode, the required area increases compared that of a typical layout. Thus, we propose a zigzag layout technique for the cell-based diode to reduce the area and obtain a high ESD survival level. To verify the feasibility of the zigzag layout techniques for cell-based diodes, we designed ESD diodes using 110[Formula: see text]nm RF CMOS technology. The experimental results successfully demonstrate the feasibility of the proposed method.

Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices

2001 ◽  
Vol 41 (9-10) ◽  
pp. 1385-1390 ◽  
Author(s):  
M. Litzenberger ◽  
R. Pichler ◽  
S. Bychikhin ◽  
D. Pogany ◽  
E. Gornik ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Single Finger ◽  
Protection Devices
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