Clock Signal and Data Recovery Unit Modeling Based on Phase-Locked-Frequency Scheme

In many VLSIs, full amplitude CMOS drivers are used for information transfer via unterminated line. What is more, path length decreases carrying capacity of such interconnection in a greater degree than CMOS drivers’ performance. Because transmit channel considerably garbles transferred information, prevailing solution to this problem are clock data recovery blocks the role of which is to retrieve data along with recovering clock signal. In this work, the process of constructing a clock signal and data recovery unit based on a single-loop phase-locked-frequency scheme that does not require a reference periodic signal is considered. The development of its behavioral model was carried out in the Verilog-AMS hardware description language, and the block modeling at the transistor level was carried out in the 90 nm CMOS technology. In this case, the recovery time was 4.8 microseconds, and the «jitter» indicator of clock signal recovery unit was 7.6 ps. The obtained values of developed clock signal and data recovery unit’s output parameters are up to the best foreign analogues.

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A Clock and Data Recovery Circuit for Optical Communications in 0.18 m CMOS

Jornada de Jóvenes Investigadores del I3A ◽

10.26754/jji-i3a.201201798 ◽

1970 ◽

pp. 19

Author(s):

C. Sánchez-Azqueta ◽

S. Celma

Keyword(s):

Optical Communications ◽

Data Stream ◽

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Clock Signal ◽

Communications Networks ◽

Power Characteristics ◽

Correct Performance ◽

Global Communications

The amount of data transmitted over the global communications networks has experienced a dramatic increase over the last years, mainly driven by the exponential growth of the Internet. For this reason, increasingly faster and more reliable circuits are needed to allow a correct performance at speeds in the range of the Gbps. The superior power characteristics and overall performance make optical fiber the preferred choice to implement the channel in communications links, giving rise to the concept of optical communications. Due to their bandwidth limitations, in a typical optical communcations link data cannot be transmitted with a timing reference; the clock signal that allows its correct interpretation has to be extracted at the receiver in a block called clock and data recovery circuit (CDR). Typically, a CDR circuit is a closed-loop system that generates an oscillating signal capable of tracking the phase of the incoming data stream; as well, it uses the generated clock signal to regenerate the data stream, minimising the effects of non-idealities during transmission. This paper presents the design of a CDR circuit intended to meet the 10GBase-LX4 Ethernet specifications for continuous operation at 3.125 GHz, designed in a standard 0.18 m CMOS technology provided by UMC. A detailed description of the full CDR circuit and the different blocks taking part in it will be provided, emphasising the requirements that each of them must satisfy. Finally, the correct performance of the proposed CDR circuit will be analysed by means of an extensive set of post-layout simulations.

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A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2008.2008520 ◽

2009 ◽

Vol 56 (1) ◽

pp. 6-10 ◽

Cited By ~ 22

Author(s):

Young-Suk Seo ◽

Jang-Woo Lee ◽

Hong-Jung Kim ◽

Changsik Yoo ◽

Jae-Jin Lee ◽

...

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.385-386.1278 ◽

2013 ◽

Vol 385-386 ◽

pp. 1278-1281 ◽

Cited By ~ 1

Author(s):

Zheng Fei Hu ◽

Ying Mei Chen ◽

Shao Jia Xue

Keyword(s):

Optical Communication ◽

Input Data ◽

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Phase Detector ◽

Voltage Controlled Oscillator ◽

Output Data ◽

Data Phase ◽

Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

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