scholarly journals Silicon Photonic Reconfigurable Optical Add-Drop Module Design (Project Report CIAN2-3-Y2)

2022 ◽  
Author(s):  
Shayan Mookherjee

Reports of a project “Silicon Photonics and Manufacturing” under the Thrust 2 “Subsystem Integration and Silicon Nanophotonics” of an NSF-funded Centre for Integrated Access Networks.

2022 ◽  
Author(s):  
Shayan Mookherjee

This was a project “Silicon Photonics Device Manufacturing and Test” under the re-organized Thrust 2 “Subsystem Integration and Silicon Nanophotonics” of an NSF-funded Center. This is a report of the 2nd generation ROADM (reconfigurable optical add drop multiplexer) device made using silicon photonics, including passive and doped silicon waveguides and metalization.


2022 ◽  
Author(s):  
Shayan Mookherjee

A multi-university partnership led by UCSD collaborated with Sandia National Labs in an NSF-funded silicon photonics multi-project wafer (MPW) project. This is a report of the ROADM +VOA (reconfigurable optical add drop multiplexer + variable optical attenuator) device made using silicon photonics, including passive and doped silicon waveguides and metalization.


2022 ◽  
Author(s):  
Shayan Mookherjee

This was a project under the Thrust 2 “Subsystem Integration and Silicon Nanophotonics” of the NSF-funded Center. The goal of this research was to design, fabricate and test microchip-scale silicon photonic components for optical WDM (wavelength division multiplexed) add/drop functionality in access and data networks. This chip was intended for use in a campus ring network.


Nanophotonics ◽  
2020 ◽  
Vol 0 (0) ◽  
Author(s):  
Wei Shi ◽  
Ye Tian ◽  
Antoine Gervais

AbstractThe tremendous growth of data traffic has spurred a rapid evolution of optical communications for a higher data transmission capacity. Next-generation fiber-optic communication systems will require dramatically increased complexity that cannot be obtained using discrete components. In this context, silicon photonics is quickly maturing. Capable of manipulating electrons and photons on the same platform, this disruptive technology promises to cram more complexity on a single chip, leading to orders-of-magnitude reduction of integrated photonic systems in size, energy, and cost. This paper provides a system perspective and reviews recent progress in silicon photonics probing all dimensions of light to scale the capacity of fiber-optic networks toward terabits-per-second per optical interface and petabits-per-second per transmission link. Firstly, we overview fundamentals and the evolving trends of silicon photonic fabrication process. Then, we focus on recent progress in silicon coherent optical transceivers. Further scaling the system capacity requires multiplexing techniques in all the dimensions of light: wavelength, polarization, and space, for which we have seen impressive demonstrations of on-chip functionalities such as polarization diversity circuits and wavelength- and space-division multiplexers. Despite these advances, large-scale silicon photonic integrated circuits incorporating a variety of active and passive functionalities still face considerable challenges, many of which will eventually be addressed as the technology continues evolving with the entire ecosystem at a fast pace.


Nanophotonics ◽  
2014 ◽  
Vol 3 (4-5) ◽  
pp. 205-214 ◽  
Author(s):  
Ari Novack ◽  
Matt Streshinsky ◽  
Ran Ding ◽  
Yang Liu ◽  
Andy Eu-Jin Lim ◽  
...  

AbstractRapid progress has been made in recent years repurposing CMOS fabrication tools to build complex photonic circuits. As the field of silicon photonics becomes more mature, foundry processes will be an essential piece of the ecosystem for eliminating process risk and allowing the community to focus on adding value through clever design. Multi-project wafer runs are a useful tool to promote further development by providing inexpensive, low-risk prototyping opportunities to academic and commercial researchers. Compared to dedicated silicon manufacturing runs, multi-project-wafer runs offer cost reductions of 100× or more. Through OpSIS, we have begun to offer validated device libraries that allow designers to focus on building systems rather than modifying device geometries. The EDA tools that will enable rapid design of such complex systems are under intense development. Progress is also being made in developing practical optical and electronic packaging solutions for the photonic chips, in ways that eliminate or sharply reduce development costs for the user community. This paper will provide a review of the recent developments in silicon photonic foundry offerings with a focus on OpSIS, a multi-project-wafer foundry service offering a silicon photonics platform, including a variety of passive components as well as high-speed modulators and photodetectors, through the Institute of Microelectronics in Singapore.


2015 ◽  
Vol 69 (9) ◽  
pp. 37-51 ◽  
Author(s):  
R. Enright ◽  
S. Lei ◽  
I. Mathews ◽  
G. Cunningham ◽  
R. Frizzell ◽  
...  

2021 ◽  
Author(s):  
Shayan Mookherjee

The main goal of this NSF-funded project [1201308 - Year 3] is to develop integrated photonics devices based on silicon photonics which can be used for compact and efficient nonlinear classical and quantum photonics applications. During the third year of this project, we demonstrated the combination of an on-chip ring mixer and a tunable filter.


2016 ◽  
Vol 41 (24) ◽  
pp. 5688 ◽  
Author(s):  
Vito Sorianello ◽  
Gabriele De Angelis ◽  
Tommaso Cassese ◽  
Massimo Valerio Preite ◽  
Philippe Velha ◽  
...  

Nanomaterials ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 1941
Author(s):  
Haike Zhu ◽  
Sean Anderson ◽  
Nick Karfelt ◽  
Lingjun Jiang ◽  
Yunchu Li ◽  
...  

Targeting high-speed, low-cost, short-reach intra-datacenter connections, we designed and tested an integrated silicon photonic circuit as a transmitter engine. This engine can be packaged into an optical transceiver module which meets the QSFP-DD Form Factor, together with other electrical/optical components. We first present the design and performance of a high-speed silicon modulator, which had a 3-dB EO bandwidth of >40 GHz and an ER of >5 dB. We then incorporated the engine onto a test board and injected a 53.125 Gbaud PAM4 signal. Clear eye patterns were observed at the receiver with TDECQ ~3 dB for all four lanes.


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