Current Image Atomic Force Microscopy (CI-AFM) Combined with Atomic Force Probing (AFP) for Location and Characterization of Advanced Technology Node

Author(s):  
Tom X. Tong ◽  
A. N. Erickson

Abstract Many of the standard techniques of Failure Analysis (FA) are breaking down or becoming less useful as feature sizes drop below 100nm. The tenth micron milestone appears to be a fundamental limitation to many common techniques. Use of Current Image-Atomic Force Microscopy (CI-AFM) combined with Atomic Force Probing (AFP) brings about a combination of technologies, which allow for extension of FA below the nano-scale.

Author(s):  
Chuan Zhang ◽  
Esther P.Y. Chen

Abstract A variety of parametric test structures were designed with the purpose of characterizing parameters tied to failure modes for specific structures, and the electrical test of the parametric test structures are typically conducted earlier inline, which could be months ahead of the functional test. Due to the unique advantages, conductive-atomic force microscopy (CAFM) was introduced to parametric test structure failure analysis during advanced technology development, and has been proven to be a powerful solution to many challenging failure analysis (FA) problems. This paper uses several case studies to illustrate how CAFM can be used to successfully localize defects in challenging parametric test structures that would otherwise be invisible with conventional FA techniques.


2018 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Tanya Schaeffer ◽  
Yuting Wei ◽  
Satish Kodali ◽  
Chong Khiam Oh

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.


Author(s):  
Willian Silva Conceição ◽  
Ştefan Ţălu ◽  
Robert Saraiva Matos ◽  
Glenda Quaresma Ramos ◽  
Fidel Guereiro Zayas ◽  
...  

2017 ◽  
Author(s):  
Lindong Zhai ◽  
Jeong Woong Kim ◽  
Jiyun Lee ◽  
Jaehwan Kim

2014 ◽  
Vol 64 (6) ◽  
pp. 923-928 ◽  
Author(s):  
D. Takeuchi ◽  
K. Makihara ◽  
A. Ohta ◽  
M. Ikeda ◽  
S. Miyazaki

Micron ◽  
2011 ◽  
Vol 42 (3) ◽  
pp. 299-304 ◽  
Author(s):  
Gi-Ja Lee ◽  
Su-Jin Chae ◽  
Jae Hoon Jeong ◽  
So-Ra Lee ◽  
Sang-Jin Ha ◽  
...  

1994 ◽  
Vol 76 (6) ◽  
pp. 3443-3447 ◽  
Author(s):  
J. M. Yáñez‐Limón ◽  
F. Ruiz ◽  
J. González‐Hernández ◽  
C. Vázquez‐López ◽  
E. López‐Cruz

2005 ◽  
Vol 77 (2) ◽  
pp. 424-434 ◽  
Author(s):  
Phillip S. Dobson ◽  
John M. R. Weaver ◽  
Mark N. Holder ◽  
Patrick R. Unwin ◽  
Julie V. Macpherson

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