Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

2018 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Tanya Schaeffer ◽  
Yuting Wei ◽  
Satish Kodali ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Scanning Capacitance Microscopy ◽  
Force Microscopy ◽  
Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

Obtaining Low Contact Resistance for Physical Sub-Micron Fault Isolation

2003 ◽  
Author(s):  
C. A. Waggoner ◽  
D. Smith
Keyword(s):  
Atomic Force Microscopy ◽  
Sample Preparation ◽  
Contact Resistance ◽  
Failure Analysis ◽  
Deep Submicron ◽  
Careful Consideration ◽  
Fault Isolation ◽  
Force Microscopy ◽  
Current Technology ◽  
Atomic Force

Abstract The continued application and extension of Moore’s is Law driving semiconductor development into the deep submicron range. 90nm processes are pushing the limits of current technology, and announcements for 65nm and even smaller process developments are common place. Inspection and deprocessing tools are pacing these developments with moderate levels of success [1]. Fault isolation, however, and particularly physical fault isolation at these levels represents perhaps the most daunting of challenges facing today’s semiconductor companies. Possibly the most important failure analysis step, physical fault isolation of sub-micron devices, is growing increasingly more challenging. Traditional probe stations find limitation below 500nm feature sizes. Recent approaches to probing smaller geometries, such as AFM (Atomic Force Microscopy), have come up short in flexibility and applicability. Deposition of FIB pads can change circuit characteristics, is costly and time consuming, and is becoming increasingly more difficult as proximities decrease. Successful probing of structures smaller than 300nm require careful consideration to reduce and stabilize contact resistance (RC). A NANO-100TM probe station with SEM optics was used to analyze characteristics of, and the process needed to obtain stable, low RC for physical submicron fault isolation. Main discussion topics include probe tip oxidation, test timing and sample preparation. Probe tip selection, probe scrub, and attack angle are also mentioned. Recommendations and findings are presented for immediate application. It is shown that if the proper steps and considerations are made, stable RC of less than 10V is possible when probing sub-micron devices.

Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

2017 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Cmos Technology ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Conductive Atomic Force Microscopy ◽  
Isolation Technique ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Atomic Force ◽  
Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Indentation modulus and hardness of viscoelastic thin films by atomic force microscopy: A case study

2009 ◽  
Vol 109 (12) ◽  
pp. 1417-1427 ◽  
Author(s):  
D. Passeri ◽  
A. Bettucci ◽  
A. Biagioni ◽  
M. Rossi ◽  
A. Alippi ◽  
...  
Keyword(s):  
Thin Films ◽  
Atomic Force Microscopy ◽  
Indentation Modulus ◽  
Force Microscopy ◽  
Atomic Force
Sign in / Sign up

Export Citation Format

Share Document