scholarly journals An Overview of Spintronic True Random Number Generator

2021 ◽  
Vol 9 ◽  
Author(s):  
Zhenxiao Fu ◽  
Yi Tang ◽  
Xi Zhao ◽  
Kai Lu ◽  
Yemin Dong ◽  
...  

A True Random Number Generator is an essential component in data encryption, hardware security, physical unclonable functions, and statistical analyses. Conventional CMOS devices usually exploit the thermal noise or jitter to generate randomness, which suffers from high energy consumption, slow bit generating rate, large area, and over-complicated circuit. In this mini review, we introduce the novel physical randomness generating mechanism based on the stochastic switching behavior of magnetic tunnel junctions. As compared to CMOS technologies, the random number generator based on spintronic devices can have many inherent advantages, such as simpler structure, compact area, higher throughput, and better energy-efficiency. Here, we review and compare various existing schemes at the device and circuit levels to achieve high performance magnetic tunnel junctions based on a True Random Number Generator. Future research trends and challenges are also discussed to stimulate more works in this area.

SPIN ◽  
2019 ◽  
Vol 09 (03) ◽  
pp. 1940009
Author(s):  
Akio Fukushima ◽  
Kay Yakushiji ◽  
Hitoshi Kubota ◽  
Hiroshi Imamura ◽  
Shinji Yuasa

We have developed a random-number-generator (RNG) named “spin dice,” which employs the stochastic nature of spin-torque switching (STS) in a magnetic tunnel junction. The principle of the idea is that the switching probability first tuned around 0.5 is varied linearly with the applied current. After that, the switching results are converted into binary random numbers. We fabricated several types of “spin dice” by combining magnetic tunnel junctions and single-board microcomputer, and achieved generation speed of random numbers up to several hundred kbit/sec. Because STS is scalable and magnetic tunnel junctions have compatibility to semiconductor fabrication process, “spin dice” can be considered as a promising candidate for truly random-number-generator (TRNG) for security applications.


2020 ◽  
Vol 14 (7) ◽  
pp. 1001-1011
Author(s):  
Dhirendra Kumar ◽  
Rahul Anand ◽  
Sajai Vir Singh ◽  
Prasanna Kumar Misra ◽  
Ashok Srivastava ◽  
...  

2021 ◽  
pp. 2100062
Author(s):  
Kyung Seok Woo ◽  
Jaehyun Kim ◽  
Janguk Han ◽  
Jin Myung Choi ◽  
Woohyun Kim ◽  
...  

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


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