scholarly journals Hardware-Based Run-Time Code Integrity in Embedded Devices

Cryptography ◽  
2018 ◽  
Vol 2 (3) ◽  
pp. 20 ◽  
Author(s):  
Taimour Wehbe ◽  
Vincent Mooney ◽  
David Keezer
Keyword(s):  
Memory System ◽  
Main Memory ◽  
Time Code ◽  
Embedded Devices ◽  
Software Vulnerabilities ◽  
Integrity Checking ◽  
Code Integrity ◽  
Run Time ◽  
Kernel Level ◽  
Level Process

Attacks on embedded devices are becoming more and more prevalent, primarily due to the extensively increasing plethora of software vulnerabilities. One of the most dangerous types of these attacks targets application code at run-time. Techniques to detect such attacks typically rely on software due to the ease of implementation and integration. However, these techniques are still vulnerable to the same attacks due to their software nature. In this work, we present a novel hardware-assisted run-time code integrity checking technique where we aim to detect if executable code resident in memory is modified at run-time by an adversary. Specifically, a hardware monitor is designed and attached to the device’s main memory system. The monitor creates page-based signatures (hashes) of the code running on the system at compile-time and stores them in a secure database. It then checks for the integrity of the code pages at run-time by regenerating the page-based hashes (with data segments zeroed out) and comparing them to the legitimate hashes. The goal is for any modification to the binary of a user-level or kernel-level process that is resident in memory to cause a comparison failure and lead to a kernel interrupt which allows the affected application to halt safely.

Routine run-time code generation

2003 ◽  
Vol 38 (12) ◽  
pp. 44-56 ◽  
Author(s):  
Sam Kamin
Keyword(s):  
Code Generation ◽  
Time Code ◽  
Run Time

Design and Run Time Code Compression for Embedded Systems

2007 ◽  
pp. 97-128
Author(s):  
Sri Parameswaran ◽  
Jörg Henkel ◽  
Andhi Janapsatya ◽  
Talal Bonny ◽  
Aleksandar Ignjatovic
Keyword(s):  
Embedded Systems ◽  
Time Code ◽  
Code Compression ◽  
Run Time

scholarly journals CP-NAS: Child-Parent Neural Architecture Search for 1-bit CNNs

2020 ◽  
Author(s):  
Li'an Zhuo ◽  
Baochang Zhang ◽  
Hanlin Chen ◽  
Linlin Yang ◽  
Chen Chen ◽  
...  
Keyword(s):  
Computational Cost ◽  
Unified Framework ◽  
Embedded Devices ◽  
Natural Approach ◽  
Neural Architecture ◽  
Resource Limited ◽  
Training Stage ◽  
Comparable Accuracy ◽  
Kernel Level ◽  
High Computational Cost

Neural architecture search (NAS) proves to be among the best approaches for many tasks by generating an application-adaptive neural architectures, which are still challenged by high computational cost and memory consumption. At the same time, 1-bit convolutional neural networks (CNNs) with binarized weights and activations show their potential for resource-limited embedded devices. One natural approach is to use 1-bit CNNs to reduce the computation and memory cost of NAS by taking advantage of the strengths of each in a unified framework. To this end, a Child-Parent model is introduced to a differentiable NAS to search the binarized architecture(Child) under the supervision of a full-precision model (Parent). In the search stage, the Child-Parent model uses an indicator generated by the parent and child model accuracy to evaluate the performance and abandon operations with less potential. In the training stage, a kernel level CP loss is introduced to optimize the binarized network. Extensive experiments demonstrate that the proposed CP-NAS achieves a comparable accuracy with traditional NAS on both the CIFAR and ImageNet databases. It achieves an accuracy of 95.27% on CIFAR-10, 64.3% on ImageNet with binarized weights and activations, and a 30% faster search than prior arts.

scholarly journals Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2158
Author(s):  
Jeong-Geun Kim ◽  
Shin-Dug Kim ◽  
Su-Kyung Yoon
Keyword(s):  
Performance Status ◽  
Random Access ◽  
Memory Systems ◽  
Memory System ◽  
Main Memory ◽  
Learning Method ◽  
Q Learning ◽  
Data Intensive ◽  
Big Data Applications ◽  
Non Volatile Memory

This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

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