Development of an Open PXIe System based on FPGA Modules

<p>PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe platform comprises of modules that are housed in a 3U Eurocard form factor chassis. The platform utilise the PCIe bus standard to enable high-speed data transfer, suitable for a range of applications. However, the platform is inherently complex, contains proprietary IP and is prohibitively expensive for most researchers and engineers who wish to utilise a modular instrumentation system. To overcome these barriers, the beginnings of an open PXIe platform has been developed. This consists of two open PXIe modules utilising modular FPGA technology. The first module is the System Controller, which introduces an embedded Linux solution and open-source PCIe driver to the platform. To simplify software development, user applications can utilise the drivers API without using kernel-level code. On the System Controller FPGA fabric is a root-port implementation that allows communication with peripheral modules. The second modules is a general purpose Peripheral Module that provides various I/O standards that users can utilise in their FPGA design, and a dedicated PCIe generation 2 x4 link with the System Controller. In the FPGA fabric of the Peripheral Module is a PCIe-DMA engine that facilitates data transfer between the two modules. The open nature and modular design will allow more economical and more flexible solutions, which will be appealing to a wide range of potential users. In addition, an example user application is developed for this system to show case the overall functionality the modules, with transfer speeds of 100 MB/s.</p>

Development of an Open PXIe System based on FPGA Modules

<p>PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe platform comprises of modules that are housed in a 3U Eurocard form factor chassis. The platform utilise the PCIe bus standard to enable high-speed data transfer, suitable for a range of applications. However, the platform is inherently complex, contains proprietary IP and is prohibitively expensive for most researchers and engineers who wish to utilise a modular instrumentation system. To overcome these barriers, the beginnings of an open PXIe platform has been developed. This consists of two open PXIe modules utilising modular FPGA technology. The first module is the System Controller, which introduces an embedded Linux solution and open-source PCIe driver to the platform. To simplify software development, user applications can utilise the drivers API without using kernel-level code. On the System Controller FPGA fabric is a root-port implementation that allows communication with peripheral modules. The second modules is a general purpose Peripheral Module that provides various I/O standards that users can utilise in their FPGA design, and a dedicated PCIe generation 2 x4 link with the System Controller. In the FPGA fabric of the Peripheral Module is a PCIe-DMA engine that facilitates data transfer between the two modules. The open nature and modular design will allow more economical and more flexible solutions, which will be appealing to a wide range of potential users. In addition, an example user application is developed for this system to show case the overall functionality the modules, with transfer speeds of 100 MB/s.</p>

Multimodal MR Images-Based Diagnosis of Early Adolescent Attention-Deficit/Hyperactivity Disorder Using Multiple Kernel Learning

Attention-deficit/hyperactivity disorder (ADHD) is one of the most common brain diseases among children. The current criteria of ADHD diagnosis mainly depend on behavior analysis, which is subjective and inconsistent, especially for children. The development of neuroimaging technologies, such as magnetic resonance imaging (MRI), drives the discovery of brain abnormalities in structure and function by analyzing multimodal neuroimages for computer-aided diagnosis of brain diseases. This paper proposes a multimodal machine learning framework that combines the Boruta based feature selection and Multiple Kernel Learning (MKL) to integrate the multimodal features of structural and functional MRIs and Diffusion Tensor Images (DTI) for the diagnosis of early adolescent ADHD. The rich and complementary information of the macrostructural features, microstructural properties, and functional connectivities are integrated at the kernel level, followed by a support vector machine classifier for discriminating ADHD from healthy children. Our experiments were conducted on the comorbidity-free ADHD subjects and covariable-matched healthy children aged 9–10 chosen from the Adolescent Brain and Cognitive Development (ABCD) study. This paper is the first work to combine structural and functional MRIs with DTI for early adolescents of the ABCD study. The results indicate that the kernel-level fusion of multimodal features achieves 0.698 of AUC (area under the receiver operating characteristic curves) and 64.3% of classification accuracy for ADHD diagnosis, showing a significant improvement over the early feature fusion and unimodal features. The abnormal functional connectivity predictors, involving default mode network, attention network, auditory network, and sensorimotor mouth network, thalamus, and cerebellum, as well as the anatomical regions in basal ganglia, are found to encode the most discriminative information, which collaborates with macrostructure and diffusion alterations to boost the performances of disorder diagnosis.

EZIOTracer

Tracing is a popular method for evaluating, investigating, and modeling the performance of today's storage systems. Tracing has become crucial with the increase in complexity of modern storage applications/systems, that are manipulating an ever-increasing amount of data and are subject to extreme performance requirements. There exists many tracing tools focusing either on the user-level or the kernel-level, however we observe the lack of a unified tracer targeting both levels: this prevents a comprehensive understanding of modern applications' storage performance profiles. In this paper, we present EZIOTracer, a unified I/O tracer for both (Linux) kernel and user spaces, targeting data intensive applications. EZIOTracer is composed of a userland as well as a kernel space tracer, complemented with a trace analysis framework able to merge the output of the two tracers, and in particular to relate user-level events to kernel-level ones, and vice-versa. On the kernel side, EZIOTracer relies on eBPF to offer safe, low-overhead, low memory footprint, and flexible tracing capabilities. We demonstrate using FIO benchmark the ability of EZIOTracer to track down I/O performance issues by relating events recorded at both the kernel and user levels. We show that this can be achieved with a relatively low overhead that ranges from 2% to 26% depending on the I/O intensity.

Characteristic features of the kernel-level rootkit for learning-based detection model training

Fast track article for IS&T International Symposium on Electronic Imaging 2021: Mobile Devices and Multimedia: Enabling Technologies, Algorithms, and Applications 2021 proceedings.

Resource Modification On Multicore Server With Kernel Bypass

Technology develops very fast marked by many innovations both from hardware and software. Multicore servers with a growing number of cores require efficient software. Kernel and Hardware used to handle various operational needs have some limitations. This limitation is due to the high level of complexity especially in handling as a server such as single socket discriptor, single IRQ and lack of pooling so that it requires some modifications. The Kernel Bypass is one of the methods to overcome the deficiencies of the kernel. Modifications on this server are a combination increase throughput and decrease server latency. Modifications at the driver level with hashing rx signal and multiple receives modification with multiple ip receivers, multiple thread receivers and multiple port listener used to increase throughput. Modifications using pooling principles at either the kernel level or the program level are used to decrease the latency. This combination of modifications makes the server more reliable with an average throughput increase of 250.44% and a decrease in latency 65.83%.