Low-Complexity Nonlinear Self-Inverse Permutation for Creating Physically Clone-Resistant Identities

Cryptography ◽  
2020 ◽  
Vol 4 (1) ◽  
pp. 6 ◽  
Author(s):  
Saleh Mulhem ◽  
Ayoub Mars ◽  
Wael Adi
Keyword(s):  
Field Programmable Gate Arrays ◽  
Low Complexity ◽  
System On Chip ◽  
Large Classes ◽  
Physical Unclonable Functions ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Security Levels ◽  
On Chip

New large classes of permutations over ℤ 2 n based on T-Functions as Self-Inverting Permutation Functions (SIPFs) are presented. The presented classes exhibit negligible or low complexity when implemented in emerging FPGA technologies. The target use of such functions is in creating the so called Secret Unknown Ciphers (SUC) to serve as resilient Clone-Resistant structures in smart non-volatile Field Programmable Gate Arrays (FPGA) devices. SUCs concepts were proposed a decade ago as digital consistent alternatives to the conventional analog inconsistent Physical Unclonable Functions PUFs. The proposed permutation classes are designed and optimized particularly to use non-consumed Mathblock cores in programmable System-on-Chip (SoC) FPGA devices. Hardware and software complexities for realizing such structures are optimized and evaluated for a sample expected target FPGA technology. The attained security levels of the resulting SUCs are evaluated and shown to be scalable and usable even for post-quantum crypto systems.

Real-time audio signal processing using system-on-chip field programmable gate arrays

2019 ◽  
Vol 146 (4) ◽  
pp. 2879-2879
Author(s):  
Ross K. Snider ◽  
Trevor Vannoy ◽  
James Eaton ◽  
Matthew Blunt ◽  
E. Bailey Galacci ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Audio Signal ◽  
Field Programmable Gate Arrays ◽  
System On Chip ◽  
Audio Signal Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

scholarly journals Implementation of an ARM-based system using a Xilinx ZYNQ SoC

2019 ◽  
Vol 13 (2) ◽  
pp. 485
Author(s):  
Omar Salem Baans ◽  
Asral Bahari Jambek
Keyword(s):  
Embedded Systems ◽  
Field Programmable Gate Arrays ◽  
System On Chip ◽  
Software System ◽  
Gate Arrays ◽  
Arm Processor ◽  
Systems On Chip ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

scholarly journals New Mathblocks-Based Feistel-Like Ciphers for Creating Clone-Resistant FPGA Devices

Cryptography ◽  
2019 ◽  
Vol 3 (4) ◽  
pp. 28 ◽  
Author(s):  
Saleh Mulhem ◽  
Wael Adi
Keyword(s):  
Hard Core ◽  
Major Elements ◽  
Physical Unclonable Functions ◽  
Mapping Functions ◽  
The Public ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Near Future

The Secret Unknown Cipher (SUC) concept was introduced a decade ago as a promising technique for creating pure digital clone-resistant electronic units as alternatives to the traditional non-consistent Physical Unclonable Functions (PUFs). In this work, a very special unconventional cipher design is presented. The design uses hard-core FPGA (Field Programmable Gate Arrays) -Mathblocks available in modern system-on-chip (SoC) FPGAs. Such Mathblocks are often not completely used in many FPGA applications; therefore, it seems wise to make use of such dead (unused) modules to fabricate usable physical security functions for free. Standard cipher designs usually avoid deploying multipliers in the cipher mapping functions due to their high complexity. The main target of this work is to design large cipher classes (e.g., cipher class size >2600) by mainly deploying the FPGA specific mathematical cores. The proposed cipher designs are novel hardware-oriented and new in the public literature, using fully new unusual mapping functions. If a random unknown selection of one cipher out of 2600 ciphers is self-configured in a device, then a Secret Unknown Cipher module is created within a device, making it physically hard to clone. We consider the cipher module for free (for zero cost) if the major elements in the cipher module are making use of unused reanimated Mathblocks. Such ciphers are usable in many future mass products for protecting vehicular units against cloning and modeling attacks. The required self-reconfigurable devices for that concept are not available now; however, they are expected to emerge in the near future.

scholarly journals Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays

2014 ◽  
Vol 22 (2) ◽  
pp. 344-356 ◽  
Author(s):  
Yohei Hori ◽  
Hyunho Kang ◽  
Toshihiro Katashita ◽  
Akashi Satoh ◽  
Shinichi Kawamura ◽  
...  
Keyword(s):  
Field Programmable Gate Arrays ◽  
Physical Unclonable Functions ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
28 Nm
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