scholarly journals High-Efficient Syndrome-Based LDPC Reconciliation for Quantum Key Distribution

Entropy ◽  
2021 ◽  
Vol 23 (11) ◽  
pp. 1440
Author(s):  
Hao-Kun Mao ◽  
Yu-Cheng Qiao ◽  
Qiong Li
Keyword(s):  
Quantum Key Distribution ◽  
Information Leakage ◽  
Key Distribution ◽  
Channel Noise ◽  
Low Density ◽  
Parity Check ◽  
Promising Technique ◽  
Low Density Parity Check ◽  
High Efficient ◽  
Simulation Results

Quantum key distribution (QKD) is a promising technique to share unconditionally secure keys between remote parties. As an essential part of a practical QKD system, reconciliation is responsible for correcting the errors due to the quantum channel noise by exchanging information through a public classical channel. In the present work, we propose a novel syndrome-based low-density parity-check (LDPC) reconciliation protocol to reduce the information leakage of reconciliation by fully utilizing the syndrome information that was previously wasted. Both theoretical analysis and simulation results show that our protocol can evidently reduce the information leakage as well as the number of communication rounds.

scholarly journals Multiedge-type low-density parity-check codes for continuous-variable quantum key distribution

2021 ◽  
Vol 103 (6) ◽  
Author(s):  
Hossein Mani ◽  
Tobias Gehring ◽  
Philipp Grabenweger ◽  
Bernhard Ömer ◽  
Christoph Pacher ◽  
...  
Keyword(s):  
Quantum Key Distribution ◽  
Key Distribution ◽  
Continuous Variable ◽  
Low Density ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Parity Check Codes

Information reconciliation for QKD

2011 ◽  
Vol 11 (3&4) ◽  
pp. 226-238
Author(s):  
David Elkouss ◽  
Jesus Martinez-Mateo ◽  
Vicente Martin
Keyword(s):  
Quantum Key Distribution ◽  
Key Agreement ◽  
Information Leakage ◽  
Error Rates ◽  
Parity Check ◽  
Random String ◽  
Secret Key ◽  
Information Reconciliation ◽  
Low Density Parity Check ◽  
Secret Key Agreement

Quantum key distribution (QKD) relies on quantum and classical procedures in order to achieve the growing of a secret random string ---the key--- known only to the two parties executing the protocol. Limited intrinsic efficiency of the protocol, imperfect devices and eavesdropping produce errors and information leakage from which the set of measured signals ---the raw key--- must be stripped in order to distill a final, information theoretically secure, key. The key distillation process is a classical one in which basis reconciliation, error correction and privacy amplification protocols are applied to the raw key. This cleaning process is known as information reconciliation and must be done in a fast and efficient way to avoid cramping the performance of the QKD system. Brassard and Salvail proposed a very simple and elegant protocol to reconcile keys in the secret-key agreement context, known as \textit{Cascade}, that has become the de-facto standard for all QKD practical implementations. However, it is highly interactive, requiring many communications between the legitimate parties and its efficiency is not optimal, imposing an early limit to the maximum tolerable error rate. In this paper we describe a low-density parity-check reconciliation protocol that improves significantly on these problems. The protocol exhibits better efficiency and limits the number of uses of the communications channel. It is also able to adapt to different error rates while remaining efficient, thus reaching longer distances or higher secure key rate for a given QKD system.

FPGA Implementation of a Novel Multi-Rate QC-LDPC Encoder for DTMB Standard

2013 ◽  
Vol 397-400 ◽  
pp. 2024-2027
Author(s):  
Fei Wang ◽  
Peng Zhang ◽  
Chang Yin Liu
Keyword(s):  
Power Consumption ◽  
Ldpc Codes ◽  
Fpga Implementation ◽  
Type I ◽  
Low Density ◽  
Parity Check ◽  
Encoding Scheme ◽  
Low Density Parity Check ◽  
Memory Resource ◽  
Simulation Results

A serial-input serial-output encoder based on pipelined type I rotate-left-accumulator (RLA) circuit is presented for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Digital Terrestrial Multimedia Broadcasting (DTMB) standard. This encoding scheme can reduce the power consumption and save memory resource. FPGA implementation and simulation results show that the design meets the requirement of DTMB standard and simplifies the structure of the memory.

scholarly journals High performance error correction for quantum key distribution using polar codes

2014 ◽  
Vol 14 (3&4) ◽  
pp. 329-338
Author(s):  
Paul Jouguet ◽  
Sebastien Kunz-Jacques
Keyword(s):  
Quantum Key Distribution ◽  
High Performance ◽  
Key Distribution ◽  
Polar Codes ◽  
Continuous Variables ◽  
Parity Check ◽  
Graphic Processing Units ◽  
Central Processing ◽  
Low Density Parity Check ◽  
Performance Error

We study the use of polar codes for both discrete and continuous variables Quantum Key Distribution (QKD). Although very large blocks must be used to obtain the efficiency required by quantum key distribution, and especially continuous variables quantum key distribution, their implementation on generic x86 Central Processing Units (CPUs) is practical. Thanks to recursive decoding, they exhibit excellent decoding speed, much higher than large, irregular Low Density Parity Check (LDPC) codes implemented on similar hardware, and competitive with implementations of the same codes on high-end Graphic Processing Units (GPUs).

Study on a New Joint Source-Channel Decoder Design

2013 ◽  
Vol 340 ◽  
pp. 471-475
Author(s):  
Fei Zhong ◽  
Shu Xu Guo
Keyword(s):  
Iterative Decoding ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Information Redundancy ◽  
Low Density Parity Check ◽  
Error Ratio ◽  
Bit Error Ratio ◽  
Simulation Results ◽  
Decoder Design

To improve upon the Low-Density Parity-Check (LDPC) codes , incorporating compressed sensing (CS) and information redundancy, a new joint decoding algorithm frame is presented. The proposed system exploits the information redundancy by CS reconstruction during the iterative decoding process to correct decoding of LDPC codes. The simulation results show that the algorithm presented can improve system decoding performance and obviously make bit error ratio (BER) lower then traditional LDPC codes. In addition, a relatively short argument is given on different CS reconstructed algorithms in proposed system, the new design is shown to benefit from different CS reconstructed algorithms.

scholarly journals A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-8
Author(s):  
M. Revathy ◽  
R. Saravanan
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Fourth Generation ◽  
Low Density ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Variable Node ◽  
High Efficient ◽  
Decoder Architecture

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

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