scholarly journals An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 816
Author(s):  
Yongrui Li ◽  
He Chen ◽  
Yizhuang Xie
Keyword(s):  
Real Time ◽  
Large Scale ◽  
High Efficiency ◽  
Imaging System ◽  
Path Delay ◽  
Real Time Processing ◽  
Time Processing ◽  
Fft Processor ◽  
Adjustment Strategy ◽  
Field Programmable

Spaceborne synthetic aperture radar (SAR) plays an important role in many fields of national defense and the national economy, and the Fast Fourier Transform (FFT) processor is an important part of the spaceborne real-time SAR imaging system. How to meet the increasing demand for ultra-large-scale data processing and to reduce the scale of the hardware platform while ensuring real-time processing is a major problem for real-time processing of on-orbit SAR. To solve this problem, in this study, we propose a 128k-point fixed-point FFT processor based on Field-Programmable Gate Array (FPGA) with a four-channel Single-path Delay Feedback (SDF) structure. First, we combine the radix-23 and mixed-radix algorithms to propose a four-channel processor structure, to achieve high efficiency hardware resources and high real-time performance. Secondly, we adopt the SDF structure combined with the radix-23 algorithm to achieve efficient use of storage resources. Third, we propose a word length adjustment strategy to ensure the accuracy of calculations. The experimental results show that the relative error between the processor and the MATLAB calculation result is maintained at about 10−4, which has good calculation accuracy.

A Real-Time Processing System Based on Field Programmable Gate Array for Infrared Image

2009 ◽  
Vol 36 (2) ◽  
pp. 307-311
Author(s):  
罗凤武 Luo Fengwu ◽  
王利颖 Wang Liying ◽  
涂霞 Tu Xia ◽  
陈厚来 Chen Houlai
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Infrared Image ◽  
Processing System ◽  
Real Time Processing ◽  
Time Processing ◽  
Field Programmable ◽  
Gate Array

A Digital Signal Processing Module for Time-Division Multiplexed Microcalorimeter Arrays

2013 ◽  
Vol 23 (3) ◽  
pp. 2500305-2500305 ◽  
Author(s):  
H Tan ◽  
M Walby ◽  
W Hennig ◽  
W Warburton ◽  
P Grudberg ◽  
...  
Keyword(s):  
Real Time ◽  
Digital Signal ◽  
Real Time Processing ◽  
Time Processing ◽  
The Core ◽  
Field Programmable ◽  
Processing Module ◽  
Time Division ◽  
Signal Processing Module ◽  
Processor Board

We have developed a digital signal processing module for real time processing of time-division multiplexed data from SQUID-coupled transition-edge sensor microcalorimeter arrays. It is a 3U PXI card consisting of a standardized core processor board and a daughter board. Through fiber-optic links on its front panel, the daughter board receives time-division multiplexed data (comprising error and feedback signals) and clocks from the digital-feedback cards developed at the National Institute of Standards and Technology. After mixing the error signal with the feedback signal in a field-programmable gate array, the daughter board transmits demultiplexed data to the core processor. Real-time processing in the field-programmable gate array of the core processor board includes pulse detection, pileup inspection, pulse height computation, and histogramming into on-board spectrum memory. Data from up to 128 microcalorimeter pixels can be processed by a single module in real time. Energy spectra, waveform, and run statistics data can be read out in real time through the PCI bus by a host computer at a maximum rate of ~100 MB/s. The module's hardware architecture, mechanism for synchronizing with NIST's digital-feedback, and count rate capability are presented.

scholarly journals On-chip data organization and access strategy for spaceborne SAR real-time imaging processor

2021 ◽  
Vol 39 (1) ◽  
pp. 126-134
Author(s):  
Shiyu Wang ◽  
Shengbing Zhang ◽  
Xiaoping Huang ◽  
Hao Lyu
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Imaging System ◽  
Data Organization ◽  
Real Time Processing ◽  
Time Processing ◽  
Chip Data ◽  
Application Systems ◽  
Sar Imaging ◽  
On Chip

Spaceborne SAR(synthetic aperture radar) imaging requires real-time processing of enormous amount of input data with limited power consumption. Designing advanced heterogeneous array processors is an effective way to meet the requirements of power constraints and real-time processing of application systems. To design an efficient SAR imaging processor, the on-chip data organization structure and access strategy are of critical importance. Taking the typical SAR imaging algorithm-chirp scaling algorithm-as the targeted algorithm, this paper analyzes the characteristics of each calculation stage engaged in the SAR imaging process, and extracts the data flow model of SAR imaging, and proposes a storage strategy of cross-region cross-placement and data sorting synchronization execution to ensure FFT/IFFT calculation pipelining parallel operation. The memory wall problem can be alleviated through on-chip multi-level data buffer structure, ensuring the sufficient data providing of the imaging calculation pipeline. Based on this memory organization and access strategy, the SAR imaging pipeline process that effectively supports FFT/IFFT and phase compensation operations is therefore optimized. The processor based on this storage strategy can realize the throughput of up to 115.2 GOPS, and the energy efficiency of up to 254 GOPS/W can be achieved by implementing 65 nm technology. Compared with conventional CPU+GPU acceleration solutions, the performance to power consumption ratio is increased by 63.4 times. The proposed architecture can not only improve the real-time performance, but also reduces the design complexity of the SAR imaging system, which facilitates excellent performance in tailoring and scalability, satisfying the practical needs of different SAR imaging platforms.

Sign in / Sign up

Export Citation Format

Share Document