scholarly journals A Task Parameter Inference Framework for Real-Time Embedded Systems

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 116
Author(s):  
Namyong Jung ◽  
Hyeongboo Baek ◽  
Jinkyu Lee

While recent studies addressed security attacks in real-time embedded systems, most of them assumed prior knowledge of parameters of periodic tasks, which is not realistic under many environments. In this paper, we address how to infer task parameters, from restricted information obtained by simple system monitoring. To this end, we first develop static properties that are independent of inference results and therefore applied only once in the beginning. We further develop dynamic properties each of which can tighten inference results by feeding an update of the inference results obtained by other properties. Our simulation results demonstrate that the proposed inference framework infers task parameters for RM (Rate Monotonic) with reasonable tightness; the ratio of exactly inferred task periods is 95.3% and 65.6%, respectively with low and high task set use. The results also discover that the inference performance varies with the monitoring interval length and the task set use.

2013 ◽  
Vol 373-375 ◽  
pp. 1168-1171 ◽  
Author(s):  
Hong Yan Lv ◽  
Fang Liu

Snowfall process is analyzed from the perspective of computer simulation in this paper, the dynamic properties and the static properties of snow particles are abstracted based on particle system theory. The snow particles movement is simulated with wind and no wind. To solve the problems of the blur of snowing environment and firn phenomena, the paper puts forward a method of applying pulverization to snowing virtual environment. The tests show that the simulation methods of snowfall and pulverization are effective and real, which are suit for real-time virtual environment.


2014 ◽  
Vol 945-949 ◽  
pp. 3380-3383
Author(s):  
Feng Xiang Zhang

This paper focus on the dynamic server algorithms, and the servers are used for scheduling soft aperiodic tasks. Many types of servers and their schedulability analysis are reviewed, these properties can be used for constructing hierarchical embedded systems, where the soft aperiodic tasks and the hard real-time tasks can be scheduled in the same system. The aperiodic tasks in the server are not preemptable, and they are executed in a first-come first-served (FCFS) manner. If it is not specified, there is only one server in the system, and rest of the processes in the system are ordinary periodic tasks. The servers could be scheduled by fixed priority or dynamic algorithms.


Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 13
Author(s):  
Balaji M ◽  
Chandrasekaran M ◽  
Vaithiyanathan Dhandapani

A Novel Rail-Network Hardware with simulation facilities is presented in this paper. The hardware is designed to facilitate the learning of application-oriented, logical, real-time programming in an embedded system environment. The platform enables the creation of multiple unique programming scenarios with variability in complexity without any hardware changes. Prior experimental hardware comes with static programming facilities that focus the students’ learning on hardware features and programming basics, leaving them ill-equipped to take up practical applications with more real-time constraints. This hardware complements and completes their learning to help them program real-world embedded systems. The hardware uses LEDs to simulate the movement of trains in a network. The network has train stations, intersections and parking slots where the train movements can be controlled by using a 16-bit Renesas RL78/G13 microcontroller. Additionally, simulating facilities are provided to enable the students to navigate the trains by manual controls using switches and indicators. This helps them get an easy understanding of train navigation functions before taking up programming. The students start with simple tasks and gradually progress to more complicated ones with real-time constraints, on their own. During training, students’ learning outcomes are evaluated by obtaining their feedback and conducting a test at the end to measure their knowledge acquisition during the training. Students’ Knowledge Enhancement Index is originated to measure the knowledge acquired by the students. It is observed that 87% of students have successfully enhanced their knowledge undergoing training with this rail-network simulator.


Author(s):  
Jaiganesh Balasubramanian ◽  
Sumant Tambe ◽  
Balakrishnan Dasarathy ◽  
Shrirang Gadgil ◽  
Frederick Porter ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.


2021 ◽  
Vol 20 (1) ◽  
pp. 1-26
Author(s):  
Paolo Pazzaglia ◽  
Youcheng Sun ◽  
Marco Di Natale

Sign in / Sign up

Export Citation Format

Share Document