scholarly journals Survey on Approximate Computing and Its Intrinsic Fault Tolerance

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 557 ◽  
Author(s):  
Gennaro Rodrigues ◽  
Fernanda Lima Kastensmidt ◽  
Alberto Bosio
Keyword(s):  
Fault Tolerance ◽  
Software Architecture ◽  
Execution Time ◽  
State Of The Art ◽  
High Reliability ◽  
Approximate Computing ◽  
Safety Critical ◽  
Triple Modular Redundancy ◽  
Modular Redundancy ◽  
Error Masking

This work is a survey on approximate computing and its impact on fault tolerance, especially for safety-critical applications. It presents a multitude of approximation methodologies, which are typically applied at software, architecture, and circuit level. Those methodologies are discussed and compared on all their possible levels of implementations (some techniques are applied at more than one level). Approximation is also presented as a means to provide fault tolerance and high reliability: Traditional error masking techniques, such as triple modular redundancy, can be approximated and thus have their implementation and execution time costs reduced compared to the state of the art.

Fault-tolerant digital systems development using triple modular redundancy

2017 ◽  
Vol 8 (1) ◽  
pp. 3-7 ◽  
Author(s):  
R. Şinca ◽  
CS. Szász
Keyword(s):  
Large Scale ◽  
Fault Tolerant ◽  
High Reliability ◽  
Systems Development ◽  
Digital Systems ◽  
Design Solution ◽  
Triple Modular Redundancy ◽  
Wide Range ◽  
Hardware Architectures ◽  
Modular Redundancy

The paper presents a fault-tolerant digital system design and development strategy for high reliability hardware architectures implementation. Starting from the general consideration that digital hardware systems play a key role in a large scale of control systems implementation, a triple modular redundancy (TMR) solution it is proposed for development. For this reason, the well-known 1 bit majority voter configuration has been extended and generalized to the full control bus of a digital control system. Computer simulations show that the proposed hardware solution fulfills in all the theoretical expectations and it can be used for experimental tests and implementation. The presented design solution and conclusions are well suited to generalization for a wide range of fault-tolerant digital systems development ranging from reliable and safety servo control applications up to high reliability parallel and distributed computing hardware architectures.

Scalable Triple Modular Redundancy Fault Tolerance Mechanism for MPI-Oriented Large Scale Parallel Computing

2012 ◽  
Vol 23 (4) ◽  
pp. 1022-1035
Author(s):  
Zhi-Yuan WANG ◽  
Xue-Jun YANG ◽  
Yun ZHOU
Keyword(s):  
Parallel Computing ◽  
Fault Tolerance ◽  
Large Scale ◽  
Tolerance Mechanism ◽  
Triple Modular Redundancy ◽  
Modular Redundancy

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

scholarly journals Reliability-Aware Multipath Routing of Time-Triggered Traffic in Time-Sensitive Networks

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 125
Author(s):  
Kai Huang ◽  
Xinming Wan ◽  
Ke Wang ◽  
Xiaowen Jiang ◽  
Junjian Chen ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
High Reliability ◽  
Multipath Routing ◽  
Shortest Path Routing ◽  
Industrial Networks ◽  
Negative Effect ◽  
Routing Method ◽  
No Wait ◽  
Spatial Redundancy ◽  
Unreliable Links

With the development of industrial networks, the demands for strict timing requirements and high reliability in transmission become more essential, which promote the establishment of a Time-Sensitive Network (TSN). TSN is a set of standards with the intention of extending Ethernet for safety-critical and real-time applications. In general, frame replication is used to achieve fault-tolerance, while the increased load has a negative effect on the schedule synthesis phase. It is necessary to consider schedulability and reliability jointly. In this paper, a heuristic-based routing method is proposed to achieve fault tolerance by spatial redundancy for TSNs containing unreliable links. A cost function is presented to evaluate each routing set, and a heuristic algorithm is applied to find the solution with higher schedulability. Compared to the shortest path routing, our method can improve the reliability and the success rate of no-wait scheduling by 5–15% depending on the scale of topology.

scholarly journals Fast Accurate and Automatic Brushstroke Extraction

2021 ◽  
Vol 17 (2) ◽  
pp. 1-24
Author(s):  
Yunfei Fu ◽  
Hongchuan Yu ◽  
Chih-Kuo Yeh ◽  
Tong-Yee Lee ◽  
Jian J. Zhang
Keyword(s):  
Neural Network ◽  
Efficient Algorithm ◽  
Deep Neural Network ◽  
High Efficiency ◽  
State Of The Art ◽  
High Reliability ◽  
The Other ◽  
Manual Annotation ◽  
Stroke Extraction ◽  
Art Research

Brushstrokes are viewed as the artist’s “handwriting” in a painting. In many applications such as style learning and transfer, mimicking painting, and painting authentication, it is highly desired to quantitatively and accurately identify brushstroke characteristics from old masters’ pieces using computer programs. However, due to the nature of hundreds or thousands of intermingling brushstrokes in the painting, it still remains challenging. This article proposes an efficient algorithm for brush Stroke extraction based on a Deep neural network, i.e., DStroke. Compared to the state-of-the-art research, the main merit of the proposed DStroke is to automatically and rapidly extract brushstrokes from a painting without manual annotation, while accurately approximating the real brushstrokes with high reliability. Herein, recovering the faithful soft transitions between brushstrokes is often ignored by the other methods. In fact, the details of brushstrokes in a master piece of painting (e.g., shapes, colors, texture, overlaps) are highly desired by artists since they hold promise to enhance and extend the artists’ powers, just like microscopes extend biologists’ powers. To demonstrate the high efficiency of the proposed DStroke, we perform it on a set of real scans of paintings and a set of synthetic paintings, respectively. Experiments show that the proposed DStroke is noticeably faster and more accurate at identifying and extracting brushstrokes, outperforming the other methods.

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