scholarly journals A Non-Intrusive, Traffic-Aware Prediction Framework for Power Consumption in Data Center Operations

Energies ◽  
2020 ◽  
Vol 13 (3) ◽  
pp. 663
Author(s):  
Zheng Liu ◽  
Mian Zhang ◽  
Xusheng Zhang ◽  
Yun Li
Keyword(s):  
Power Consumption ◽  
Prediction Model ◽  
Data Center ◽  
Data Centers ◽  
Prediction Performance ◽  
Coarse Grained ◽  
Fine Grained ◽  
Encoding Strategy ◽  
Power Consumption Prediction ◽  
Consumption Prediction

Modern cloud computing relies heavily on data centers, which usually host tens of thousands of servers. Predicting the power consumption accurately in data center operations is crucial for energy optimization. In this paper, we formulate the power consumption prediction at both the fine-grained and coarse-grained level. We carefully discuss the desired properties of an applicable prediction model and propose a non-intrusive, traffic-aware prediction framework for power consumption. We design a character-level encoding strategy for URIs and employ both convolutional and recurrent neural networks to develop a unified prediction model. We use real datasets to simulate requests and analyze the characteristics of the collected power consumption series. Extensive experiments demonstrate that our proposed framework can achieve superior prediction performance compared to other popular leading prediction methods.

scholarly journals Twin-Shaft Mixers’ Mechanical Behavior Numerical Simulations of the Mix and Phases

Machines ◽  
2019 ◽  
Vol 7 (2) ◽  
pp. 39 ◽  
Author(s):  
Maria Cristina Valigi ◽  
Silvia Logozzo ◽  
Luca Landi ◽  
Claudio Braccesi ◽  
Luca Galletti
Keyword(s):  
Power Consumption ◽  
Prediction Model ◽  
Mechanical Behavior ◽  
Numerical Simulations ◽  
Design Parameters ◽  
Force Estimation ◽  
Mixing Processes ◽  
Increase Productivity ◽  
Power Consumption Prediction ◽  
Consumption Prediction

In this paper, the mechanical behavior of concrete twin-shaft mixers is analyzed in terms of power consumption and exchanged forces between the mixture and the mixing organs during the mixing cycle. The mixing cycle is divided into two macro phases, named transient and regime phase, where the behavior of the mixture is modeled in two different ways. A force estimation and power consumption prediction model are presented for both the studied phases and they are validated by experimental campaigns. From the application of this model to different machines and by varying different design parameters, the optimization of the power consumption of the concrete twin-shaft mixers is analyzed. Results of this work can be used to increase productivity and profitability of concrete mixers and reduce energy waste in the industries which involve mixing processes.

scholarly journals An Electric Bus Power Consumption Model and Optimization of Charging Scheduling Concerning Multi-External Factors

Energies ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 2060 ◽  
Author(s):  
Yajing Gao ◽  
Shixiao Guo ◽  
Jiafeng Ren ◽  
Zheng Zhao ◽  
Ali Ehsan ◽  
...  
Keyword(s):  
Power Consumption ◽  
Prediction Model ◽  
Large Scale ◽  
Operating Cost ◽  
Electricity Consumption ◽  
External Factors ◽  
Electric Bus ◽  
Consumption Data ◽  
Power Consumption Prediction ◽  
Consumption Prediction

With the large scale operation of electric buses (EBs), the arrangement of their charging optimization will have a significant impact on the operation and dispatch of EBs as well as the charging costs of EB companies. Thus, an accurate grasp of how external factors, such as the weather and policy, affect the electric consumption is of great importance. Especially in recent years, haze is becoming increasingly serious in some areas, which has a prominent impact on driving conditions and resident travel modes. Firstly, the grey relational analysis (GRA) method is used to analyze the various external factors that affect the power consumption of EBs, then a characteristic library of EBs concerning similar days is established. Then, the wavelet neural network (WNN) is used to train the power consumption factors together with power consumption data in the feature library, to establish the power consumption prediction model with multiple factors. In addition, the optimal charging model of EBs is put forward, and the reasonable charging time for the EB is used to achieve the minimum operating cost of the EB company. Finally, taking the electricity consumption data of EBs in Baoding and the data of relevant factors as an example, the power consumption prediction model and the charging optimization model of the EB are verified, which provides an important reference for the optimal charging of the EB, the trip arrangement of the EB, and the maximum profit of the electric public buses.

Pre-execution power consumption prediction of computational multithreaded workloads

2014 ◽  
Vol 17 (4) ◽  
pp. 1323-1333 ◽  
Author(s):  
Hamid Fadishei ◽  
Hossein Deldari ◽  
Mahmoud Naghibzadeh
Keyword(s):  
Power Consumption ◽  
Multithreaded Workloads ◽  
Power Consumption Prediction ◽  
Consumption Prediction

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

High-Performance Reconfigurable Computing

2018 ◽  
pp. 4018-4029
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.

scholarly journals HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Alexander Thomas ◽  
Michael Rückauer ◽  
Jürgen Becker
Keyword(s):  
Power Consumption ◽  
Reconfigurable Computing ◽  
Register Transfer Level ◽  
Coarse Grained ◽  
Fine Grained ◽  
Reconfigurable Devices ◽  
Resource Requirements ◽  
Broad Variety ◽  
And Performance ◽  
Reconfigurable Hardware Architecture

Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.

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