scholarly journals Synchronous Counter Design Using Novel Level Sensitive T-FF in QCA Technology

2019 ◽  
Vol 9 (3) ◽  
pp. 27 ◽  
Author(s):  
Majeed ◽  
Alkaldy ◽  
bin Zainal ◽  
Bin MD Nor
Keyword(s):  
Cellular Automata ◽  
Power Analysis ◽  
Logic Gates ◽  
Low Power Consumption ◽  
Flip Flop ◽  
Optimal Form ◽  
Quantum Dot Cellular Automata ◽  
Computer Scientists ◽  
Simulation Results ◽  
Qca Circuits

The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and for presenting logic gates in an optimal structure. The T flip-flop, which is an essential part of digital designs, can be used to design synchronous and asynchronous counters. This paper presents a novel T flip-flop structure in an optimal form. The presented novel gate was used to design an N-bit binary synchronous counter. The QCADesigner software was used to verify the designed circuits and to present the simulation results, while the QCAPro tool was used for the power analysis. The proposed design required minimal power and showed good improvements over previous designs.

scholarly journals Design of Falling-Edge Triggered T Flip-Flop based on Quantum-Dot Cellular Automata

2018 ◽  
Vol 7 (4.4) ◽  
pp. 19 ◽  
Author(s):  
Young Won You ◽  
Jun Cheol Jeon
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Pulse Generator ◽  
Essential Element ◽  
Clock Pulse ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Clock Pulse Generator ◽  
Qca Circuits

A T flip-flop, which is an essential element of a counter, has been proposed as various types of quantum-dot cellular automata (QCA) circuits, but practicality is not expected because there is no clock in circuit. A T flip-flop is a circuit which outputs value changing in synchronization with the rising or falling edge of a clock. In a QCA circuit, a clock pulse generator outputs the time at which the clock changes and it is required for the circuit. In this paper, we propose a falling-edge triggered T flip-flop based on QCA.  

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Design of Efficient and Testable n-Input Logic Gates in Quantum-Dot Cellular Automata

2013 ◽  
Vol 10 (10) ◽  
pp. 2347-2353 ◽  
Author(s):  
Samira Sayedsalehi ◽  
Mohammad Hossein Moaiyeri ◽  
Keivan Navi
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gates ◽  
Quantum Dot Cellular Automata

Designing layout–timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony

2007 ◽  
Vol 53 (9) ◽  
pp. 551-567 ◽  
Author(s):  
Myungsu Choi ◽  
Zachary Patitz ◽  
Byoungjae Jin ◽  
Feng Tao ◽  
Nohpill Park ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
Qca Circuits

scholarly journals Cellular Automaton Belousov–Zhabotinsky Model for Binary Full Adder

2017 ◽  
Vol 27 (06) ◽  
pp. 1750089 ◽  
Author(s):  
Nikolaos I. Dourvas ◽  
Georgios Ch. Sirakoulis ◽  
Andrew Adamatzky
Keyword(s):  
Cellular Automata ◽  
Cellular Automaton ◽  
Logic Gates ◽  
Full Adder ◽  
Wave Fronts ◽  
Excitation Wave ◽  
Bz Reaction ◽  
Computer Scientists ◽  
Oregonator Model ◽  
Logic Unit

The continuous increment in the performance of classical computers has been driven to its limit. New ways are studied to avoid this oncoming bottleneck and many answers can be found. An example is the Belousov–Zhabotinsky (BZ) reaction which includes some fundamental and essential characteristics that attract chemists, biologists, and computer scientists. Interaction of excitation wave-fronts in BZ system, can be interpreted in terms of logical gates and applied in the design of unconventional hardware components. Logic gates and other more complicated components have been already proposed using different topologies and particular characteristics. In this study, the inherent parallelism and simplicity of Cellular Automata (CAs) modeling is combined with an Oregonator model of light-sensitive version of BZ reaction. The resulting parallel and computationally-inexpensive model has the ability to simulate a topology that can be considered as a one-bit full adder digital component towards the design of an Arithmetic Logic Unit (ALU).

Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata

2018 ◽  
Vol 14 (1) ◽  
pp. 38-48 ◽  
Author(s):  
Fahimeh Danehdaran ◽  
Milad Bagherian Khosroshahy ◽  
Keivan Navi ◽  
Nader Bagherzadeh
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Analysis ◽  
Full Adder ◽  
Quantum Dot Cellular Automata

scholarly journals Novel Design for Quantum Dots Cellular Automata to Obtain Fault-Tolerant Majority Gate

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Razieh Farazkish ◽  
Samira Sayedsalehi ◽  
Keivan Navi
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Fault Tolerant ◽  
Electrostatic Energy ◽  
Majority Gate ◽  
Quantum Dot Cellular Automata ◽  
Dislocation Cells ◽  
The Difference ◽  
Qca Circuits ◽  
Novel Design

Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.

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