scholarly journals Design of a 1-Bit MEMS Gyroscope Using the Model Predictive Control Approach

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 730 ◽  
Author(s):  
Xiaofeng Wu ◽  
Zhicheng Xie ◽  
Xueliang Bai ◽  
Trevor Kwan
Keyword(s):  
Model Predictive Control ◽  
Predictive Control ◽  
Signal To Noise Ratio ◽  
Signal To Noise ◽  
Mems Gyroscope ◽  
Control Approach ◽  
Delta Sigma Modulator ◽  
Hard Constraints ◽  
Delta Sigma ◽  
Computational Requirement

In this paper, a bi-level Delta-Sigma modulator-based MEMS gyroscope design is presented based on a Model Predictive Control (MPC) approach. The MPC is popular because of its capability of handling hard constraints. In this work, we propose to combine the 1-bit nature of the bi-level Delta-Sigma modulator output with the MPC to develop a 1-bit processing-based MPC (OBMPC). This paper will focus on the affine relationship between the 1-bit feedback and the in-loop MPC controller, as this can potentially remove the multipliers from the controller. In doing so, the computational requirement of the MPC control is significantly alleviated, which makes the 1-bit MEMS Gyroscope feasible for implementation. In addition, a stable constrained MPC is designed, so that the input will not overload the quantizer while maintaining a higher Signal-to-Noise Ratio (SNR).

A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Complex Coefficient ◽  
Loop Filter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

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