scholarly journals ACE: ARIA-CTR Encryption for Low-End Embedded Processors

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3788 ◽  
Author(s):  
Hwajeong Seo ◽  
Hyeokdong Kwon ◽  
Hyunji Kim ◽  
Jaehoon Park
Keyword(s):  
Diffusion Layer ◽  
High Speed ◽  
Block Cipher ◽  
Embedded Processors ◽  
Embedded Processor ◽  
Modes Of Operation ◽  
Risc Processor ◽  
Mode Of Operation ◽  
Security Levels

In this paper, we present the first optimized implementation of ARIA block cipher on low-end 8-bit Alf and Vegard’s RISC processor (AVR) microcontrollers. To achieve high-speed implementation, primitive operations, including rotation operation, a substitute layer, and a diffusion layer, are carefully optimized for the target low-end embedded processor. The proposed ARIA implementation supports the electronic codebook (ECB) and the counter (CTR) modes of operation. In particular, the CTR mode of operation is further optimized with the pre-computed table of two add-round-key, one substitute layer, and one diffusion layer operations. Finally, the proposed ARIA-CTR implementations on 8-bit AVR microcontrollers achieved 187.1, 216.8, and 246.6 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively. Compared with previous reference implementations, the execution timing is improved by 69.8%, 69.6%, and 69.5% for 128-bit, 192-bit, and 256-bit security levels, respectively.

scholarly journals High-Speed Implementation of PRESENT on AVR Microcontroller

Mathematics ◽  
2021 ◽  
Vol 9 (4) ◽  
pp. 374
Author(s):  
Hyeokdong Kwon ◽  
Young Beom Kim ◽  
Seog Chung Seo ◽  
Hwajeong Seo
Keyword(s):  
Diffusion Layer ◽  
High Speed ◽  
High Performance ◽  
Embedded Processors ◽  
Modes Of Operation ◽  
Avr Microcontroller ◽  
Code Book

We propose the compact PRESENT on embedded processors. To obtain high-performance, PRESENT operations, including an add-round-key, a substitute layer and permutation layer operations are efficiently implemented on target embedded processors. Novel PRESENT implementations support the Electronic Code Book (ECB) and Counter (CTR). The implementation of CTR is improved by using the pre-computation for one substitute layer, two diffusion layer, and two add-round-key operations. Finally, compact PRESENT on target microcontrollers achieved 504.2, 488.2, 488.7, and 491.6 clock cycles per byte for PRESENT-ECB, 16-bit PRESENT-CTR (RAM-based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively. Compared with former implementation, the execution timing is improved by 62.6%, 63.8%, 63.7%, and 63.5% for PRESENT-ECB, 16-bit PRESENT-CTR (RAM based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively.

scholarly journals PAGE—Practical AES-GCM Encryption for Low-End Microcontrollers

2020 ◽  
Vol 10 (9) ◽  
pp. 3131 ◽  
Author(s):  
Kyungho Kim ◽  
Seungju Choi ◽  
Hyeokdong Kwon ◽  
Hyunjun Kim ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Main Idea ◽  
Optimization Methods ◽  
Optimization Techniques ◽  
Middle Term ◽  
Risc Processor ◽  
Look Up Table ◽  
Mode Of Operation ◽  
Security Levels ◽  
The Look

An optimized AES (Advanced Encryption Standard) implementation of Galois Counter Mode of operation (GCM) on low-end microcontrollers is presented in this paper. Two optimization methods are applied to proposed implementations. First, the AES counter (CTR) mode of operation is speed-optimized and ensures constant timing. The main idea is replacing expensive AES operations, including AddRound Key, SubBytes, ShiftRows, and MixColumns, into simple look-up table access. Unlike previous works, the look-up table does not require look-up table updates during the entire encryption life-cycle. Second, the core operation of Galois Counter Mode (GCM) is optimized further by using Karatsuba algorithm, compact register utilization, and pre-computed operands. With above optimization techniques, proposed AES-GCM on 8-bit AVR (Alf and Vegard’s RISC processor) architecture from short-term, middle-term to long-term security levels achieved 415, 466, and 477 clock cycles per byte, respectively.

Design of Online Pipeline Ultrasonic Data Acquisition and Storage System Based on PCI Bus

2014 ◽  
Vol 651-653 ◽  
pp. 2296-2300
Author(s):  
Jing Huang ◽  
She Yu Zhou ◽  
Bing Lei Guan
Keyword(s):  
Data Acquisition ◽  
Ultrasonic Testing ◽  
High Speed ◽  
Storage System ◽  
Ultrasonic Signal ◽  
Pci Bus ◽  
Online Data ◽  
Embedded Processor ◽  
Design Scheme ◽  
And Storage

Based on the theory of ultrasonic testing, an online data-acquisition and storage system is designed. The design scheme of hardware and software of the system is introduced in this paper, in which the embedded processor DSP and FPGA is used as its control core and the interface of PCI bus and DSP is designed. Thus a high speed and large-capacity ultrasonic signal can be processed, furthermore the pipelines defects can be analyze and evaluate.

scholarly journals Compact and High Speed Hardware Implementation of the Block- Cipher Clefia

2016 ◽  
Vol 133 (8) ◽  
pp. 17-20
Author(s):  
V.A. Suryawanshi ◽  
G.C. Manna ◽  
S.S. Dorale
Keyword(s):  
High Speed ◽  
Hardware Implementation ◽  
Block Cipher

scholarly journals Hybrid Model in the Block Cipher Applications for High-speed Communications Networks

2020 ◽  
Vol 12 (4) ◽  
pp. 55-70
Author(s):  
Minh Nguyen Hieu ◽  
Bac Do Thi ◽  
Canh Hoang Ngoc ◽  
Manh Cong Tran ◽  
Phan Duong Phuc ◽  
...  
Keyword(s):  
Hybrid Model ◽  
High Speed ◽  
Block Cipher ◽  
Communications Networks

scholarly journals Efficient and high speed key-independent AES-based authenticated encryption architecture using FPGAs

2017 ◽  
Vol 7 (1.5) ◽  
pp. 230
Author(s):  
A. Murali ◽  
K Hari Kishore
Keyword(s):  
High Speed ◽  
Hash Functions ◽  
Data Integrity ◽  
Block Ciphers ◽  
Authenticated Encryption ◽  
Time Data ◽  
Cryptographic Primitives ◽  
Security Services ◽  
High Security ◽  
Security Levels

Data manipulations are made with the use of communication and networking systems. But at the same time, data integrity is also a needed and important property that must be maintained in every data communicating systems. For this, the security levels are provided with cryptographic primitives like hash functions and block ciphers which are deployed into the systems. For efficient architectures, FPGA-based systems like AES-GCM and AEGIS-128 plays in the best part of the re-configurability, which supports the security services of such communication and networking systems. We possibly focus on the performance of the systems with the high security of the FPGA bit streams. GF (2128) multiplier is implemented for authentication tasks for high-speed targets. And also, the implementations were evaluated by using vertex 4.5 FPGA’s

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