High-speed hardware implementations of the KASUMI block cipher

2004 ◽  
Author(s):  
P. Kitsos ◽  
M.D. Galanis ◽  
O. Koufopavlou
Keyword(s):  
High Speed ◽  
Block Cipher ◽  
Hardware Implementations

Compact Hardware Implementations of MISTY1 Block Cipher

2017 ◽  
Vol 27 (03) ◽  
pp. 1850037 ◽  
Author(s):  
Yasir ◽  
Ning Wu ◽  
Xiaoqiang Zhang
Keyword(s):  
Low Power ◽  
Block Cipher ◽  
Comprehensive Analysis ◽  
The Other ◽  
Key Generation ◽  
Round Function ◽  
Other Hand ◽  
Hardware Implementations ◽  
Covered Area

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

scholarly journals Compact and High Speed Hardware Implementation of the Block- Cipher Clefia

2016 ◽  
Vol 133 (8) ◽  
pp. 17-20
Author(s):  
V.A. Suryawanshi ◽  
G.C. Manna ◽  
S.S. Dorale
Keyword(s):  
High Speed ◽  
Hardware Implementation ◽  
Block Cipher

scholarly journals Hybrid Model in the Block Cipher Applications for High-speed Communications Networks

2020 ◽  
Vol 12 (4) ◽  
pp. 55-70
Author(s):  
Minh Nguyen Hieu ◽  
Bac Do Thi ◽  
Canh Hoang Ngoc ◽  
Manh Cong Tran ◽  
Phan Duong Phuc ◽  
...  
Keyword(s):  
Hybrid Model ◽  
High Speed ◽  
Block Cipher ◽  
Communications Networks

scholarly journals Cryptanalysis on SDDO-Based BM123-64 Designs Suitable for Various IoT Application Targets

Symmetry ◽  
2018 ◽  
Vol 10 (8) ◽  
pp. 353 ◽  
Author(s):  
Tran Phuc ◽  
Changhoon Lee
Keyword(s):  
Internet Of Things ◽  
High Speed ◽  
High Probability ◽  
Block Cipher ◽  
Algorithm Selection ◽  
Key Schedule ◽  
Boomerang Attack ◽  
Selection For ◽  
Differential Attacks

BM123-64 block cipher, which was proposed by Minh, N.H. and Bac, D.T. in 2014, was designed for high speed communication applications factors. It was constructed in hybrid controlled substitution–permutation network (CSPN) models with two types of basic controlled elements (CE) in distinctive designs. This cipher is based on switchable data-dependent operations (SDDO) and covers dependent-operations suitable for efficient primitive approaches for cipher constructions that can generate key schedule in a simple way. The BM123-64 cipher has advantages including high applicability, flexibility, and portability with different algorithm selection for various application targets with internet of things (IoT) as well as secure protection against common types of attacks, for instance, differential attacks and linear attacks. However, in this paper, we propose methods to possibly exploit the BM123-64 structure using related-key attacks. We have constructed a high probability related-key differential characteristics (DCs) on a full eight rounds of BM123-64 cipher. The related-key amplified boomerang attack is then proposed on all three different cases of operation-specific designs with effective results in complexity of data and time consumptions. This study can be considered as the first cryptographic results on BM123-64 cipher.

scholarly journals FPGA Modeling and Optimization of a SIMON Lightweight Block Cipher

Sensors ◽  
2019 ◽  
Vol 19 (4) ◽  
pp. 913 ◽  
Author(s):  
Sa’ed Abed ◽  
Reem Jaffal ◽  
Bassam Mohd ◽  
Mohammad Alshayeji
Keyword(s):  
Block Cipher ◽  
Sensitive Data ◽  
Hardware Implementations ◽  
Balancing Energy ◽  
Field Programmable ◽  
Constrained Environments ◽  
Continuous Stream ◽  
Lightweight Block Cipher ◽  
The One ◽  
Least Area

Security of sensitive data exchanged between devices is essential. Low-resource devices (LRDs), designed for constrained environments, are increasingly becoming ubiquitous. Lightweight block ciphers provide confidentiality for LRDs by balancing the required security with minimal resource overhead. SIMON is a lightweight block cipher targeted for hardware implementations. The objective of this research is to implement, optimize, and model SIMON cipher design for LRDs, with an emphasis on energy and power, which are critical metrics for LRDs. Various implementations use field-programmable gate array (FPGA) technology. Two types of design implementations are examined: scalar and pipelined. Results show that scalar implementations require 39% less resources and 45% less power consumption. The pipelined implementations demonstrate 12 times the throughput and consume 31% less energy. Moreover, the most energy-efficient and optimum design is a two-round pipelined implementation, which consumes 31% of the best scalar’s implementation energy. The scalar design that consumes the least energy is a four-round implementation. The scalar design that uses the least area and power is the one-round implementation. Balancing energy and area, the two-round pipelined implementation is optimal for a continuous stream of data. One-round and two-round scalar implementations are recommended for intermittent data applications.

A High Speed Block Cipher Algorithm

2013 ◽  
Vol 7 (6) ◽  
pp. 43-54
Author(s):  
Bac Do Thi ◽  
Minh Nguyen Hieu
Keyword(s):  
High Speed ◽  
Block Cipher

scholarly journals An Efficient Hardware Architecture with Adjustable Precision and Extensible Range to Implement Sigmoid and Tanh Functions

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1739
Author(s):  
Hui Chen ◽  
Lin Jiang ◽  
Heping Yang ◽  
Zhonghai Lu ◽  
Yuxiang Fu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Network Algorithms ◽  
Rotation Mode ◽  
Hardware Implementations ◽  
Vector Mode ◽  
First Time ◽  
Special Case ◽  
Sigmoid Functions ◽  
Case Based

The efficient and precise hardware implementations of tanh and sigmoid functions play an important role in various neural network algorithms. Different applications have different requirements for accuracy. However, it is difficult for traditional methods to achieve adjustable precision. Therefore, we propose an efficient-hardware, adjustable-precision and high-speed architecture to implement them for the first time. Firstly, we present two methods to implement sigmoid and tanh functions. One is based on the rotation mode of hyperbolic CORDIC and the vector mode of linear CORDIC (called RHC-VLC), another is based on the carry-save method and the vector mode of linear CORDIC (called CSM-VLC). We validate the two methods by MATLAB and RTL implementations. Synthesized under the TSMC 40 nm CMOS technology, we find that a special case AR∣VR(3,0), based on RHC-VLC method, has the area of 4290.98 μm2 and the power of 1.69 mW at the frequency of 1.5 GHz. However, under the same frequency, AR∣VC(3) (a special case based on CSM-VLC method) costs 3196.36 μm2 area and 1.38 mW power. They are both superior to existing methods for implementing such an architecture with adjustable precision.

scholarly journals ACE: ARIA-CTR Encryption for Low-End Embedded Processors

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3788 ◽  
Author(s):  
Hwajeong Seo ◽  
Hyeokdong Kwon ◽  
Hyunji Kim ◽  
Jaehoon Park
Keyword(s):  
Diffusion Layer ◽  
High Speed ◽  
Block Cipher ◽  
Embedded Processors ◽  
Embedded Processor ◽  
Modes Of Operation ◽  
Risc Processor ◽  
Mode Of Operation ◽  
Security Levels

In this paper, we present the first optimized implementation of ARIA block cipher on low-end 8-bit Alf and Vegard’s RISC processor (AVR) microcontrollers. To achieve high-speed implementation, primitive operations, including rotation operation, a substitute layer, and a diffusion layer, are carefully optimized for the target low-end embedded processor. The proposed ARIA implementation supports the electronic codebook (ECB) and the counter (CTR) modes of operation. In particular, the CTR mode of operation is further optimized with the pre-computed table of two add-round-key, one substitute layer, and one diffusion layer operations. Finally, the proposed ARIA-CTR implementations on 8-bit AVR microcontrollers achieved 187.1, 216.8, and 246.6 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively. Compared with previous reference implementations, the execution timing is improved by 69.8%, 69.6%, and 69.5% for 128-bit, 192-bit, and 256-bit security levels, respectively.

Hardware Implementation of AES Algorithm with Logic S-box

2017 ◽  
Vol 26 (09) ◽  
pp. 1750141 ◽  
Author(s):  
Soufiane Oukili ◽  
Seddik Bri
Keyword(s):  
Data Security ◽  
High Speed ◽  
Hardware Implementation ◽  
Network Applications ◽  
Aes Algorithm ◽  
Communication Techniques ◽  
High Speed Network ◽  
Cryptographic Algorithm ◽  
Hardware Implementations ◽  
Field Programmable

Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

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