Compact and High Speed Hardware Implementation of the Block- Cipher Clefia

Increased volumes and speed of data transmission over computer networks, and also the need to protect the transmitted data, require accordingly to increase the speed of cryptographic data processing. One of the ways to achieve high performance is implementation of FPGAs-based cryptographic equipment. Therewith, to cut the cost of equipment, it is important that encryption modules shall consume a minimum possible hardware resources. The work aims to find the most compact high-speed solution for FPGA-based Kuznyechik block cipher. Several methods for hardware implementation of linear transformation, which is used in Kuznyechik cipher, have been reviewed. Various aspects of implementation of these methods taking into account the architecture of target FPGAs are investigated. We also consider aspects of the FPGA implementation of nonlinear transformation, which is used in Kuznyechik block cipher. Resource consumption by various implemented solutions of linear transformation has been estimated. A relatively compact high-speed implemented solution of Kuznyechik block cipher has been obtained and tested on the real equipment. The achieved values of speed for iterative and fully pipelined implementations of the algorithm have been presented.

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Orthros: A Low-Latency PRF

IACR Transactions on Symmetric Cryptology ◽

10.46586/tosc.v2021.i1.37-77 ◽

2021 ◽

pp. 37-77

Author(s):

Subhadeep Banik ◽

Takanori Isobe ◽

Fukang Liu ◽

Kazuhiko Minematsu ◽

Kosei Sakamoto

Keyword(s):

Hardware Implementation ◽

Block Cipher ◽

State Of The Art ◽

Security Analysis ◽

Parallel Structure ◽

Low Latency ◽

Round Function ◽

Minimum Latency ◽

Primary Focus ◽

Pseudorandom Function

We present Orthros, a 128-bit block pseudorandom function. It is designed with primary focus on latency of fully unrolled circuits. For this purpose, we adopt a parallel structure comprising two keyed permutations. The round function of each permutation is similar to Midori, a low-energy block cipher, however we thoroughly revise it to reduce latency, and introduce different rounds to significantly improve cryptographic strength in a small number of rounds. We provide a comprehensive, dedicated security analysis. For hardware implementation, Orthros achieves the lowest latency among the state-of-the-art low-latency primitives. For example, using the STM 90nm library, Orthros achieves a minimum latency of around 2.4 ns, while other constructions like PRINCE, Midori-128 and QARMA9-128- σ0 achieve 2.56 ns, 4.10 ns, 4.38 ns respectively.

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Hybrid Model in the Block Cipher Applications for High-speed Communications Networks

International journal of Computer Networks & Communications ◽

10.5121/ijcnc.2020.12404 ◽

2020 ◽

Vol 12 (4) ◽

pp. 55-70

Author(s):

Minh Nguyen Hieu ◽

Bac Do Thi ◽

Canh Hoang Ngoc ◽

Manh Cong Tran ◽

Phan Duong Phuc ◽

...

Keyword(s):

Hybrid Model ◽

High Speed ◽

Block Cipher ◽

Communications Networks

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High-speed hardware implementations of the KASUMI block cipher

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1329330 ◽

2004 ◽

Cited By ~ 5

Author(s):

P. Kitsos ◽

M.D. Galanis ◽

O. Koufopavlou

Keyword(s):

High Speed ◽

Block Cipher ◽

Hardware Implementations

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Cryptanalysis on SDDO-Based BM123-64 Designs Suitable for Various IoT Application Targets

Symmetry ◽

10.3390/sym10080353 ◽

2018 ◽

Vol 10 (8) ◽

pp. 353 ◽

Cited By ~ 2

Author(s):

Tran Phuc ◽

Changhoon Lee

Keyword(s):

Internet Of Things ◽

High Speed ◽

High Probability ◽

Block Cipher ◽

Algorithm Selection ◽

Key Schedule ◽

Boomerang Attack ◽

Selection For ◽

Differential Attacks

BM123-64 block cipher, which was proposed by Minh, N.H. and Bac, D.T. in 2014, was designed for high speed communication applications factors. It was constructed in hybrid controlled substitution–permutation network (CSPN) models with two types of basic controlled elements (CE) in distinctive designs. This cipher is based on switchable data-dependent operations (SDDO) and covers dependent-operations suitable for efficient primitive approaches for cipher constructions that can generate key schedule in a simple way. The BM123-64 cipher has advantages including high applicability, flexibility, and portability with different algorithm selection for various application targets with internet of things (IoT) as well as secure protection against common types of attacks, for instance, differential attacks and linear attacks. However, in this paper, we propose methods to possibly exploit the BM123-64 structure using related-key attacks. We have constructed a high probability related-key differential characteristics (DCs) on a full eight rounds of BM123-64 cipher. The related-key amplified boomerang attack is then proposed on all three different cases of operation-specific designs with effective results in complexity of data and time consumptions. This study can be considered as the first cryptographic results on BM123-64 cipher.

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Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v2.i1.pp15-20 ◽

2013 ◽

Vol 2 (1) ◽

pp. 15

Author(s):

Sachin B. Jadhav ◽

Jayamala K. Patil ◽

Ramesh T. Patil

Keyword(s):

Binary Tree ◽

High Speed ◽

Hardware Implementation ◽

Critical Path ◽

Partial Product ◽

Design And Implementation ◽

Multiplication Operation ◽

Multiplication Process ◽

Major Bottleneck ◽

Speed Up

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

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