Implementasi algoritma block cipher four pada mikrokontroler STM32F103C8T6

Pada masa industri 4.0, data menjadi salah satu komponen yang wajib dilindungi. Block cipher merupakan salah satu algoritma yang digunakan untuk mengamankan data. Penelitian ini bertujuan untuk mengimplementasikan algoritma block cipher four (BCF) pada mikrokontroler. Parameter yang menjadi tolak ukur antara lain besaran flash dan RAM mikrokontroler yang terpakai, serta kecepatan eksekusi proses komputasi algoritma BCF. Mikrokontroler akan menjalankan algoritma BCF dengan urutan komputasi key-schedule, enkripsi, dan dekripsi. Setiap kali memulai proses komputasi, maka pin trigger pada mikrokontroler akan mengirimkan sinyal rising ke osiloskop dan pada saat selesai melakukan komputasi maka pin trigger mikrokontroler akan mengirimkan sinyal falling ke osiloskop. Hasil penelitian menunjukkan algoritma BCF dapat diimplementasikan pada mikrokontroler STM32F103C8T6. Flash dan RAM yang digunakan mencapai 22,02 Kb dan 5,12 Kb. Algoritma BCF yang diimplementasikan pada mikrokontroler STM32F103C8T6 mampu berjalan sampai dengan 704 kali lebih cepat jika dibandingkan dengan prosesor NIOS II, 11 kali lebih cepat dibandingkan dengan AES-Engine, dan lebih lambat 4 kali jika dibandingkan dengan BCF-Engine.

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Modification of the key schedule of the 2-GOST block cipher and its implementation on FPGA

Journal of Computer Virology and Hacking Techniques ◽

10.1007/s11416-021-00406-x ◽

2021 ◽

Author(s):

A. Dmukh ◽

D. Trifonov ◽

A. Chookhno

Keyword(s):

Block Cipher ◽

Key Schedule

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Cryptanalysis on SDDO-Based BM123-64 Designs Suitable for Various IoT Application Targets

Symmetry ◽

10.3390/sym10080353 ◽

2018 ◽

Vol 10 (8) ◽

pp. 353 ◽

Cited By ~ 2

Author(s):

Tran Phuc ◽

Changhoon Lee

Keyword(s):

Internet Of Things ◽

High Speed ◽

High Probability ◽

Block Cipher ◽

Algorithm Selection ◽

Key Schedule ◽

Boomerang Attack ◽

Selection For ◽

Differential Attacks

BM123-64 block cipher, which was proposed by Minh, N.H. and Bac, D.T. in 2014, was designed for high speed communication applications factors. It was constructed in hybrid controlled substitution–permutation network (CSPN) models with two types of basic controlled elements (CE) in distinctive designs. This cipher is based on switchable data-dependent operations (SDDO) and covers dependent-operations suitable for efficient primitive approaches for cipher constructions that can generate key schedule in a simple way. The BM123-64 cipher has advantages including high applicability, flexibility, and portability with different algorithm selection for various application targets with internet of things (IoT) as well as secure protection against common types of attacks, for instance, differential attacks and linear attacks. However, in this paper, we propose methods to possibly exploit the BM123-64 structure using related-key attacks. We have constructed a high probability related-key differential characteristics (DCs) on a full eight rounds of BM123-64 cipher. The related-key amplified boomerang attack is then proposed on all three different cases of operation-specific designs with effective results in complexity of data and time consumptions. This study can be considered as the first cryptographic results on BM123-64 cipher.

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Human-readable Proof of the Related-Key Security of AES-128

IACR Transactions on Symmetric Cryptology ◽

10.46586/tosc.v2017.i2.59-83 ◽

2017 ◽

pp. 59-83 ◽

Cited By ~ 1

Author(s):

Khoongming Khoo ◽

Eugene Lee ◽

Thomas Peyrin ◽

Siang Meng Sim

Keyword(s):

Block Cipher ◽

Internal State ◽

Meaningful Information ◽

Key Schedule ◽

Simple Permutation ◽

Computer Based ◽

First Time ◽

Truncated Differential

The related-key model is now considered an important scenario for block cipher security and many schemes were broken in this model, even AES-192 and AES-256. Recently were introduced efficient computer-based search tools that can produce the best possible related-key truncated differential paths for AES. However, one has to trust the implementation of these tools and they do not provide any meaningful information on how to design a good key schedule, which remains a challenge for the community as of today. We provide in this article the first human-readable proof on the minimal number of active Sboxes in the related-key model for AES-128, without any help from a computer. More precisely, we show that any related-key differential path for AES-128 will respectively contain at least 0, 1, 3 and 9 active Sboxes for 1, 2, 3 and 4 rounds. Our proof is tight, not trivial, and actually exhibits for the first time the interplay between the key state and the internal state of an AES-like block cipher with an AES-like key schedule. As application example, we leverage our proofs to propose a new key schedule, that is not only faster (a simple permutation on the byte positions) but also ensures a higher number of active Sboxes than AES-128’s key schedule. We believe this is an important step towards a good understanding of efficient and secure key schedule designs.

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Differential Fault Attack on KASUMI Cipher Used in GSM Telephony

Mathematical Problems in Engineering ◽

10.1155/2014/251853 ◽

2014 ◽

Vol 2014 ◽

pp. 1-7 ◽

Cited By ~ 4

Author(s):

Zongyue Wang ◽

Xiaoyang Dong ◽

Keting Jia ◽

Jingyuan Zhao

Keyword(s):

Time Complexity ◽

Block Cipher ◽

Fault Attack ◽

Key Schedule ◽

Cellular Telephony ◽

Differential Fault Attack

The confidentiality of GSM cellular telephony depends on the security of A5 family of cryptosystems. As an algorithm in this family survived from cryptanalysis, A5/3 is based on the block cipher KASUMI. This paper describes a novel differential fault attack on KAUSMI with a 64-bit key. Taking advantage of some mathematical observations on the FL, FO functions, and key schedule, only one 16-bit word fault is required to recover all information of the 64-bit key. The time complexity is only 232encryptions. We have practically simulated the attack on a PC which takes only a few minutes to recover all the key bits. The simulation also experimentally verifies the correctness and complexity.

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Block cipher four implementation on field programmable gate array

Communications in Science and Technology ◽

10.21924/cst.5.2.2020.184 ◽

2020 ◽

Vol 5 (2) ◽

pp. 53-64

Author(s):

Yusuf Kurniawan ◽

Muhammad Adli Rizqulloh

Keyword(s):

Information Systems ◽

Embedded Systems ◽

Efficient Method ◽

Field Programmable Gate Array ◽

Block Cipher ◽

Input Output ◽

Nios Ii ◽

Design And Implementation ◽

Field Programmable ◽

Host Processor

Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.

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Automated Search Oriented to Key Recovery on Ciphers with Linear Key Schedule

IACR Transactions on Symmetric Cryptology ◽

10.46586/tosc.v2021.i2.249-291 ◽

2021 ◽

pp. 249-291

Author(s):

Lingyue Qin ◽

Xiaoyang Dong ◽

Xiaoyun Wang ◽

Keting Jia ◽

Yunwen Liu

Keyword(s):

High Probability ◽

Block Cipher ◽

Secret Key ◽

Key Recovery ◽

Key Schedule ◽

Before And After ◽

Two Phases ◽

Key Recovery Attack ◽

Key Recovery Attacks ◽

Automated Search

Automatic modelling to search distinguishers with high probability covering as many rounds as possible, such as MILP, SAT/SMT, CP models, has become a very popular cryptanalysis topic today. In those models, the optimizing objective is usually the probability or the number of rounds of the distinguishers. If we want to recover the secret key for a round-reduced block cipher, there are usually two phases, i.e., finding an efficient distinguisher and performing key-recovery attack by extending several rounds before and after the distinguisher. The total number of attacked rounds is not only related to the chosen distinguisher, but also to the extended rounds before and after the distinguisher. In this paper, we try to combine the two phases in a uniform automatic model.Concretely, we apply this idea to automate the related-key rectangle attacks on SKINNY and ForkSkinny. We propose some new distinguishers with advantage to perform key-recovery attacks. Our key-recovery attacks on a few versions of round-reduced SKINNY and ForkSkinny cover 1 to 2 more rounds than the best previous attacks.

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A simple power analysis attack against the key schedule of the Camellia block cipher

Information Processing Letters ◽

10.1016/j.ipl.2005.03.013 ◽

2005 ◽

Vol 95 (3) ◽

pp. 409-412 ◽

Cited By ~ 7

Author(s):

Lu Xiao ◽

Howard M. Heys

Keyword(s):

Power Analysis ◽

Block Cipher ◽

Key Schedule ◽

Simple Power ◽

Power Analysis Attack

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Fast implementations of ARX-based lightweight block ciphers (SPARX, CHAM) on 32-bit processor

International Journal of Distributed Sensor Networks ◽

10.1177/1550147719874180 ◽

2019 ◽

Vol 15 (9) ◽

pp. 155014771987418 ◽

Cited By ~ 2

Author(s):

Byoungjin Seok ◽

Changhoon Lee

Keyword(s):

Execution Time ◽

Block Cipher ◽

Block Ciphers ◽

Memory Usage ◽

Resource Constrained ◽

Word Size ◽

Key Schedule ◽

Round Function ◽

Fast Implementation ◽

Implementation Method

Recently, many lightweight block ciphers are proposed, such as PRESENT, SIMON, SPECK, Simeck, SPARX, GIFT, and CHAM. Most of these ciphers are designed with Addition–Rotation–Xor (ARX)-based structure for the resource-constrained environment because ARX operations can be implemented efficiently, especially in software. However, if the word size of a block cipher is smaller than the register size of the target device, it may process inefficiently in the aspect of memory usage. In this article, we present a fast implementation method for ARX-based block ciphers, named two-way operation. Moreover, also we applied SPARX-64/128 and CHAM-64/128 and estimated the performance in terms of execution time (cycles per byte) on a 32-bit Advanced RISC Machines processor. As a result, we achieved a large amount of improvement in execution time. The cycles of round function and key schedule are reduced by 53.31% and 31.51% for SPARX-64/128 and 41.22% and 19.40% for CHAM-64/128.

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