Energy-Efficient Optical Interconnects in Cloud Computing Infrastructures

2013 ◽  
pp. 224-240 ◽  
Author(s):  
Christoforos Kachris ◽  
Ioannis Tomkos
Keyword(s):  
Cloud Computing ◽  
Power Consumption ◽  
Interconnection Networks ◽  
Optical Interconnects ◽  
High Performance ◽  
Interconnection Network ◽  
Research Literature ◽  
Optical Interconnection ◽  
High Bandwidth ◽  
Cloud Infrastructures

This chapter discusses the rise of optical interconnection networks in cloud computing infrastructures as a novel alternative to current networks based on commodity switches. Optical interconnects can significantly reduce the power consumption and meet the future network traffic requirements. Additionally, this chapter presents some of the most recent and promising optical interconnects architectures for high performance data centers that have appeared recently in the research literature. Furthermore, it presents a qualitative categorization of these schemes based on their main features such as performance, connectivity, and scalability, and discusses how these architectures could provide green cloud infrastructures with reduced power consumption. Finally, the chapter presents a case study of an optical interconnection network that is based on high-bandwidth optical OFDM links and shows the reduction of the energy consumption that it can achieve in a typical data center.

Energy-Efficient Optical Interconnects in Cloud Computing Infrastructures

2013 ◽  
pp. 463-478
Author(s):  
Christoforos Kachris ◽  
Ioannis Tomkos
Keyword(s):  
Cloud Computing ◽  
Power Consumption ◽  
Interconnection Networks ◽  
Optical Interconnects ◽  
High Performance ◽  
Interconnection Network ◽  
Research Literature ◽  
Optical Interconnection ◽  
High Bandwidth ◽  
Cloud Infrastructures

This chapter discusses the rise of optical interconnection networks in cloud computing infrastructures as a novel alternative to current networks based on commodity switches. Optical interconnects can significantly reduce the power consumption and meet the future network traffic requirements. Additionally, this chapter presents some of the most recent and promising optical interconnects architectures for high performance data centers that have appeared recently in the research literature. Furthermore, it presents a qualitative categorization of these schemes based on their main features such as performance, connectivity, and scalability, and discusses how these architectures could provide green cloud infrastructures with reduced power consumption. Finally, the chapter presents a case study of an optical interconnection network that is based on high-bandwidth optical OFDM links and shows the reduction of the energy consumption that it can achieve in a typical data center.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Cloud Computing for Scientific Simulation and High Performance Computing

2013 ◽  
pp. 51-70
Author(s):  
Adrian Jackson ◽  
Michèle Weiland
Keyword(s):  
Cloud Computing ◽  
High Performance Computing ◽  
High Performance ◽  
Large Scale ◽  
Parallel Programs ◽  
Small Scale ◽  
Cloud Infrastructure ◽  
Scientific Simulations ◽  
Cloud Infrastructures ◽  
Performance Computing

This chapter describes experiences using Cloud infrastructures for scientific computing, both for serial and parallel computing. Amazon’s High Performance Computing (HPC) Cloud computing resources were compared to traditional HPC resources to quantify performance as well as assessing the complexity and cost of using the Cloud. Furthermore, a shared Cloud infrastructure is compared to standard desktop resources for scientific simulations. Whilst this is only a small scale evaluation these Cloud offerings, it does allow some conclusions to be drawn, particularly that the Cloud can currently not match the parallel performance of dedicated HPC machines for large scale parallel programs but can match the serial performance of standard computing resources for serial and small scale parallel programs. Also, the shared Cloud infrastructure cannot match dedicated computing resources for low level benchmarks, although for an actual scientific code, performance is comparable.

Green Computing

2014 ◽  
pp. 248-260
Keyword(s):  
Climate Change ◽  
Cloud Computing ◽  
High Performance Computing ◽  
High Performance ◽  
Large Scale ◽  
Green Computing ◽  
Research Topic ◽  
The Other ◽  
Cloud Infrastructures ◽  
Performance Computing

Green computing is a contemporary research topic to address climate and energy challenges. In this chapter, the authors envision the duality of green computing with technological trends in other fields of computing such as High Performance Computing (HPC) and cloud computing on one hand and economy and business on the other hand. For instance, in order to provide electricity for large-scale cloud infrastructures and to reach exascale computing, we need huge amounts of energy. Thus, green computing is a challenge for the future of cloud computing and HPC. Alternatively, clouds and HPC provide solutions for green computing and climate change. In this chapter, the authors discuss this proposition by looking at the technology in detail.

FACILITATING HIGH-PERFORMANCE IMAGE ANALYSIS ON REDUCED HYPERCUBE (RH) PARALLEL COMPUTERS

1995 ◽  
Vol 09 (04) ◽  
pp. 679-698 ◽  
Author(s):  
SOTIRIOS G. ZIAVRAS ◽  
MICHALIS A. SIDERAS
Keyword(s):  
Image Analysis ◽  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Parallel Computers ◽  
Number Of Publications ◽  
Low Dimensional ◽  
High Level ◽  
The Cost ◽  
Cube Connected Cycles

The direct binary hypercube interconnection network has been very popular for the design of parallel computers, because it provides a low diameter and can emulate efficiently the majority of the topologies frequently employed in the development of algorithms. The last fifteen years have seen major efforts to develop image analysis algorithms for hypercube-based parallel computers. The results of these efforts have culminated in a large number of publications included in prestigious scholarly journals and conference proceedings. Nevertheless, the aforementioned powerful properties of the hypercube come at the cost of high VLSI complexity due to the increase in the number of communication ports and channels per PE (processing element) with an increase in the total number of PE’s. The high VLSI complexity of hypercube systems is undoubtedly their dominant drawback; it results in the construction of systems that contain either a large number of primitive PE’s or a small number of powerful PE’s. Therefore, low-dimensional k-ary n-cubes with lower VSLI complexity have recently drawn the attention of many designers of parallel computers. Alternative solutions reduce the hypercube’s VLSI complexity without jeopardizing its performance. Such an effort by Ziavras has resulted in the introduction of reduced hypercubes (RH’s). Taking advantage of existing high-performance routing techniques, such as wormhole routing, an RH is obtained by a uniform reduction in the number of edges for each hypercube node. An RH can also be viewed as several connected copies of the well-known cube-connected-cycles network. The objective here is to prove that parallel computers comprising RH interconnection networks are definitely good choices for all levels of image analysis. Since the exact requirements of high-level image analysis are difficult to identify, but it is believed that versatile interconnection networks, such as the hypercube, are suitable for relevant tasks, we investigate the problem of emulating hypercubes on RH’s. The ring (or linear array), the torus (or mesh), and the binary tree are the most frequently used topologies for the development of algorithms in low-level and intermediate-level image analysis. Thus, to prove the viability of the RH for the two lower levels of image analysis, we introduce techniques for embedding the aforementioned three topologies into RH’s. The results prove the suitability of RH’s for all levels of image analysis.

BROADCASTING IN BUS INTERCONNECTION NETWORKS

2000 ◽  
Vol 01 (02) ◽  
pp. 73-94
Author(s):  
A. FERREIRA ◽  
A. GOLDMAN ◽  
S. W. SONG
Keyword(s):  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Parallel Architectures ◽  
Interprocessor Communication ◽  
Efficient Manner ◽  
Graph Theoretic ◽  
Communication Algorithms ◽  
Communication Links ◽  
Point To Point

In most distributed memory MIMD multiprocessors, processors are connected by a point-to-point interconnection network, usually modeled by a graph where processors are nodes and communication links are edges. Since interprocessor communication frequently constitutes serious bottlenecks, several architectures were proposed that enhance point-to-point topologies with the help of multiple bus systems so as to improve the communication efficiency. In this paper we study parallel architectures where the communication means are constituted solely by buses. These architectures can use the power of bus technologies, providing a way to interconnect much more processors in a simple and efficient manner. We present the hyperpath, hypergrid, hyperring, and hypertorus architectures, which are the bus-based versions of the well used point-to-point interconnection networks. Using (hyper) graph theoretic concepts to model inter-processor communication in such networks, we give optimal algorithms for broadcasting a message from one processor to all the others. For deriving high performance communication patterns we developed a new tool called simplification. The idea is to construct a graph, to be called representative graph, from the original hyper-topology, in such a way that it will become easy to describe and perform communication schemes to the former that will fit to the latter, because the simplification concept also allows us to partially use some already known communication algorithms for usual networks.

A Fast Fault-Identification Algorithm Tailored for Optical Interconnection Networks in High-Performance Computers

2014 ◽  
Vol 936 ◽  
pp. 2307-2312
Author(s):  
He Li
Keyword(s):  
Interconnection Networks ◽  
Decomposition Method ◽  
High Performance ◽  
Fault Identification ◽  
Optical Interconnection ◽  
Identification Algorithm ◽  
Cycle Decomposition ◽  
Diagnosis Algorithm ◽  
High Performance Computers

Due to integrated positive features of both hypercube and tori, optical multi-mesh hypercube (OMMH) networks in high-performance computers are regarded as a class of promising optical inter-connection networks. This paper firstly derive that the diagnosability of OMMH under the pessimistic strategy is (2n+6)/(2n+6), which shows that the OMMH possesses strong self-diagnosingability. With the improved cycle decomposition method by Yang in J. Parall. Distrib. Comput. [10], a fast diagnosis algorithm to identify all faulty nodes tailored for OMMH, which runs in O(Nlog2N) time is also proposed, where N is the number of the processors of an OMMH.

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